[Atria Development Board AT32F421 Review] - Peripheral Review
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[Atria Development Board AT32F421 Review] - Peripheral Review
AT32F421 is a lightweight M4 core microcontroller. It has a high frequency and basic peripherals to meet basic software design requirements. It has an 18 -channel ADC, IAP-enabled EFLASH memory, SPI, I2C, DMA, CRC, USART, etc. As an algorithm application engineer, these are the main things I use .
AT32F421 Introduction:
The AT32F421 series of microcontrollers include the ARM CortexTM-M4 processor core, bus architecture, peripherals and memory. The CortexTM-M4 processor is a new-age core with many advanced features. Compared to the CortexTM-M3 , the CortexTM-M4 processor supports an enhanced and efficient DSP instruction set, including an extended single-cycle 16/32- bit multiplication and accumulation ( MAC ), dual 16 -bit MAC instructions, optimized 8/16- bit SIMD operations and saturation operation instructions. When the CortexTM-M4 with DSP function is used in the design, it can be particularly energy-saving and faster than software solutions, making the CortexTM-M4 suitable for product markets that require microcontrollers to provide high performance and low power consumption.
1. Embedded Flash Controller (EFC)
FLASH can be used to implement ICP and IAP, and can also meet the needs of offline data storage in projects.
The embedded flash memory can be programmed using either In-Circuit Programming ( ICP ) or In-Application Programming ( IAP ). In-Circuit Programming (ICP ) is used to update the entire contents of the flash memory by downloading the user application to the microcontroller via the SWD protocol or the system loader ( bootloader ). In-Application Programming (IAP ) , in contrast to ICP , allows downloading programs or data to the memory using any of the communication interfaces supported by the microcontroller (such as I/O ports, UART , I2C , SPI , etc.). IAP allows the user to re . However, IAP requires that at least part of the program has been burned into the flash memory using ICP . The flash interface implements access to instructions and data on the AHB protocol, which speeds up memory access by pre-fetching the memory ; the flash interface also implements the logic required to program and erase the flash memory at all operating voltages, including access and write protection and control of the select byte.
Arteli's FLASH routine read and write test:
Here is the main program:
Before writing to FLASH, perform array assignment, then run the write FLASH function, and check the corresponding data of the test memory address of memory1 during simulation to see that it is the assigned data.
Then run the FLASH read function
is the data written and the test is completed. Overall, writing and reading are still very convenient and accurate.
2. CRC calculation unit ( CRC )
The Arteli CRC calculation unit contains a 32 - bit data register that can be read and written. During the CRC calculation, the CPU write operation will be suspended , so the register CRC_DR can be written back-to-back or continuously written - read .
The cyclic redundancy check ( CRC ) calculation unit obtains the CRC calculation result of any 32- bit full word based on a fixed generator polynomial . In other applications, CRC technology is mainly used to verify the correctness and integrity of data transmission or data storage. Standard EN/IEC 60335-1 provides a method for verifying the integrity of flash memory. The CRC calculation unit can calculate the software identification when the program is running, and then compare it with the reference identification generated during connection, and then store it in the specified memory space.
Official routine:
The function can be called directly to read the CRC check result.
The AT32F421 has an ultra-low power comparator COMP built in , which can be used as a standalone device ( all interfaces are provided on the I/O ) or with a fixed
Used in conjunction with a timer.
Comparators can be used for a variety of functions, including:
Wake up from low power mode triggered by analog signal
Analog signal conditioning
When used in conjunction with the PWM output of the timer , it forms a cycle-by-cycle current control loop
The comparators have rail-to-rail inputs and fast or slow modes, each comparator has a configurable positive input and a configurable negative input for flexible voltage selection, programmable speed / power, programmable hysteresis output, the output can be redirected to I/O or timer input for triggering the following events , the comparator has a blanked output, and the comparator can generate an interrupt to wake up the device from sleep mode and stop mode ( through the EXTI controller ).
The following figure is a comparator block diagram:
When I/Os are used as comparator inputs, they must be configured in analog mode in the GPIOs register. The comparator outputs can be connected to the I/Os using the alternate function channels given in the " Alternate Function Mapping " table of the data sheet . The outputs can be redirected internally to the inputs of various timers used for the following purposes. The comparator can be used for safety purposes such as overcurrent or thermal protection. For applications with specific functional safety requirements, it must be ensured that the programming of the comparator cannot be changed in the event of an unexpected register access or program counter corruption. The purpose of the output blanking function of the comparator is to prevent the current regulation from tripping due to the peak current generated at the start of the PWM ( usually, this peak current is present in the power switch circuit composed of anti-parallel diodes). The output blanking function is implemented by a selectable blanking window, which is derived from the output compare signal of the timer. The blanking window is configured by software (refer to the register description of the comparator to select the available blanking sources). The blanking signal is then inverted and ANDed with the comparator output to obtain the desired comparator output.
4. Infrared Transmitter ( IRTMR )
Infrared transmitters are relatively rare to me, or maybe I have never used them, so this review has broadened my horizons.
The infrared interface is used to control the LED that emits infrared light . The LED can be used to transmit infrared data to realize infrared remote control. TMR16_OC1 , USART1 , USART2 and TMR17_OC1 are connected internally. TMR16_OC1/USART1/USART2 (selected by the IR_MOD[1 : 0] bit in the SYSCFG_CFGR1 register ) generates a low-frequency modulation envelope signal, and TMR17_OC1 generates a high-frequency carrier signal to generate the required infrared control signal. The polarity control bit can be used to invert the infrared output ( IR_POL bit in the SYSCFG_CFGR1 register ). When using the infrared interface, you need to configure PB9 or PA13 to multiplex mode and enable PB9 or PA13.
Because the infrared transmitter has a fixed IO port and cannot reuse pins, pay attention to the reasonable allocation of IO port resources during use.
The following figure is a schematic diagram of the infrared internal connection:
5. MCU debugging ( MCUDBG )
The AT32F421 uses the Cortex-M4 core, which contains a hardware debug module that supports complex debugging operations. The hardware debug module allows the core to stop when fetching instructions ( instruction breakpoints ) or accessing data ( data breakpoints ) . When the core stops, the internal state of the core and the external state of the system can be queried. After the query is completed, the core and peripherals can be restored and the program will continue to execute. When the AT32F421 microcontroller is connected to a debugger and debugging begins, the debugger will use the core's hardware debug module for debugging operations. Serial debugging is supported .
Debug block diagram of AT32F421 level and Cortex-M4 level:
The MCUDBG module helps the debugger debug low power mode, timer, ERTC, I2C , WWDG and IWDG . When the corresponding bit is set, it provides clock or keeps the current state of counter timer, WWDG , IWDG or I2C in low power mode . The MCU debug module assists the debugger in providing debugging support for low power mode, providing clock control and ID code of timer, watchdog and I2C at breakpoint .
Note that the MCUDBG register image and reset value must operate these peripheral registers in word ( 32 -bit) mode.
I tried this function and it is very convenient. It also supports low power debugging, which is pretty good.
The above are more special peripherals, and the following are general ones. I will test a few of them, and their effects and stability are acceptable.
The I 2 C ( Inter-Chip ) bus interface connects the microcontroller to the serial I 2 C bus. It provides multi-master functionality and controls all I 2 C bus-specific timing, protocols, arbitration, and timing. It supports both standard and fast modes and is compatible with SMBus2.0. The I 2 C module has many uses, including CRC code generation and verification, SMBus (System Management Bus ) and PMBus ( Power Management Bus ) . Depending on the needs of the specific device , DMA can be used to reduce the burden on the CPU .
The i 2 C module receives and transmits data and converts data from serial to parallel or parallel to serial. Interrupts can be enabled or disabled. The interface connects to the I 2 C bus via the data pin (SDA) and the clock pin (SCL) . Allows connection to a standard ( up to 100kHz) or fast ( up to 400kHz) I 2 C bus .
Functional block diagram of I2C :
IIC itself can use GPIO simulation, so the priority of GPIO pin function reuse is relatively low. This IIC is a bit sour. . .
7. Serial Peripheral Interface ( SPI )
The SPI interface can be configured to support the SPI protocol or the I 2 S audio protocol. The SPI interface works in SPI mode by default, and the function can be switched from SPI mode to I 2 S mode by software. The Serial Peripheral Interface ( SPI ) allows the chip to communicate with external devices in half / full-duplex, synchronous, serial mode. This interface can be configured in master mode and provide a communication clock ( SCK ) for external slave devices. The interface can also work in multi-master configuration. It can be used for a variety of purposes, including two-wire simplex synchronous transmission using a bidirectional data line, and reliable communication using CRC check. I 2 S is also a 3- pin synchronous serial interface communication protocol. It supports four audio standards, including the Philips I 2 S standard, the MSB and LSB alignment standard, and the PCM standard. It can work in master and slave modes in half-duplex communication . When it acts as a master device, it provides a clock signal to the external slave device through the interface.
SPI features: 3- wire full-duplex synchronous transmission, 2-wire simplex synchronous transmission with or without the third bidirectional data line, 8 or 16 -bit transmission frame format selection, master or slave operation, support for multi-master mode, 10 master mode baud rate pre-scaling coefficients (maximum f PCLK /2 ), slave mode frequency (maximum fPCLK/2 ), fast communication in master mode and slave mode, NSS management by software or hardware in both master mode and slave mode : dynamic change of master / slave operation mode, programmable clock polarity and phase, programmable data order, MSB first or LSB first, dedicated send and receive flags that can trigger interrupts, SPI bus busy status flag, hardware CRC to support reliable communication, master mode fault, overload and CRC error flags that can trigger interrupts, 2- byte send and receive buffers that support DMA function : generate send and receive requests,
SPI Block Diagram:
8. Analog / Digital Conversion ( ADC )
The Arteli AT32F421 has a 12 -bit ADC which is a successive approximation analog-to-digital converter. It has up to 18 channels and can measure 15 external and 3 internal signal sources. The A/D conversion of each channel can be performed in single, continuous, scan or intermittent mode. The result of the ADC can be stored in a 16- bit data register in a left -aligned or right-aligned manner . The analog watchdog feature allows the application to detect whether the input voltage exceeds the user-defined high / low threshold. The input clock of the ADC must not exceed 28 MHz , which is generated by dividing PCLK2 .
Below is the official source code, using DMA:
The peripherals include USART, TIMER, etc., which will not be described here one by one. Please refer to the official information for details.
The official information of Yatli is still very detailed, and the layout is also very comfortable, so newcomers will not feel tired when reading it.
Finally, the official introduction to AT32F421 is released.
The AT32F421 series microcontroller uses a high-performance ARM Cortex TM -M4 32- bit RISC core with a maximum operating frequency of 120 MHz . The Cortex TM -M4 core has a set of DSP instructions and a memory protection unit ( MPU ) to improve application security. The AT32F421 series has built-in high-speed embedded memory (up to 64 K bytes of flash memory and 16 K bytes of SRAM ), rich enhanced I/O ports and peripherals connected to two APB buses. The built-in memory can set any range of program areas to be protected by sLib , becoming an execution code security library area. The device includes a 12 - bit ADC , an analog comparator, 5 general - purpose 16 -bit timers, and an advanced timer. It also includes standard and advanced communication interfaces: up to 2 I 2 C interfaces , 2 SPI interfaces (multiplexed as I 2 S interfaces), 2 USART interfaces, and 1 infrared transmitter .
The AT32F421 series is compatible with all ARM tools and software.
PS: I personally think that in order to use the M4 instead of the M3, many parameters of the Yatli official have been restricted, but it is better to be safe. The above is an excerpt and personal summary. If there are any errors or inappropriateness, please leave a message to point them out.
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