STSPIN32F0251, STSPIN32F0252
Datasheet
Advanced 250 V three-phase BLDC controller with embedded STM32 MCU
Features
•
Three-phase gate drivers
–
High voltage rail up to 250 V
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dV/dt transient immunity ±50 V/ns
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Gate driving voltage range from 9V to 20V
Driver current capability:
–
STSPIN32F0251/Q: 200/350 mA source/sink current
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STSPIN32F0252/Q: 1/0.85 A source/sink current
32-bit ARM
®
Cortex
®
-M0 core:
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Up to 48 MHz clock frequency
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4-kByte SRAM with HW parity
–
32-kByte Flash memory with option bytes
–
used for write/readout protection
21 general-purpose I/O ports (GPIO)
6 general-purpose timers
12-bit ADC converter (up to 10 channels)
I
2
C, USART and SPI interfaces
Matched propagation delay for all channels
Integrated bootstrap diodes
Comparator for fast over current protection
UVLO, Interlocking and deadtime functions
Smart shutdown (smartSD) function
Standby mode for low power consumption
On-chip debug support via SWD
Extended temperature range: -40 to +125 °C
Package:
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TQFP 10x10 64L pitch 0.5 Creepage 1.2 mm
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QFN 10x10 72L pitch 0.5 Creepage 1.8 mm
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TQFP 10x10 64L pitch 0.5
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Product status link
STSPIN32F0251
STSPIN32F0252
STSPIN32F0251Q
STSPIN32F0252Q
Product label
Applications
•
•
•
•
•
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Home and Industrial refrigerators compressors
Industrial drives, pumps, fans
Air conditioning compressors & fans
Corded power tools, garden tools
Home appliances
Industrial automation
Description
The STSPIN32F025x is a system in package providing an extremely integrated
solution suitable for driving three-phase applications.
DS13048
-
Rev 4
-
February 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
STSPIN32F0251, STSPIN32F0252
It embeds an MCU (STM32F031x6x7) featuring an ARM® 32-bit Cortex®-M0 CPU
and a 250V triple half bridge gate driver, able to drive N-channel power MOSFETs or
IGBTs.
A comparator featuring advanced smartSD function is integrated in the device,
ensuring fast and effective protection against overload and overcurrent.
The high-voltage bootstrap diodes are also integrated, as well as anti cross-
conduction (interlocking), deadtime and UVLO protection on both the lower and
upper driving sections, which prevents the power switches from operating in low
efficiency or dangerous conditions. Matched delays between low and high-side
sections guarantee no cycle distortion.
The integrated MCU allows performing FOC, 6-step sensorless and other advanced
driving algorithm including the speed control loop.
It has WR and RD protection for embedded flash memory to prevent unwanted
writing and reading, and it can be put in standby mode to reduce the power
consumption.
The MCU provides 21 general-purpose I/O ports (GPIO) with 5 V tolerant capability,
one 12-bit analog-to-digital converter with up to 10 channels performing conversions
in a single-shot or scan modes, 6 synchronizable general-purpose timers and
supports an easy to use debugging serial interface (SWD).
All of the integrated features of STSPIN32F025x make design of the application PCB
easier, and result in reduced PCB area consumption, bill of material and overall
application cost.
DS13048
-
Rev 4
page 2/32
STSPIN32F0251, STSPIN32F0252
Block diagram
1
Block diagram
Figure 1.
STSPIN32F025x SiP block diagram
PA14
PA15
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PA12
PA13
VDD
VCC
VSS
VCC
UVLO
DETECTION
UVLO
VCC
D1
EN
UV &
Level Shifter
Floating structure
VCC
D2
+5V
BOOT3
HVG3
OUT3
BOOT2
HVG2
HIN3
+5V
UV &
Level Shifter
Floating structure
+5V
VCC
D3
HIN2
OUT2
BOOT1
HVG1
V
CC
HlN1
UV &
Level Shifter
+5V
LOGIC
SHOOT
THROUGH
PREVENTION
+5V
DEADTIME
V
CC
+5V
Floating structure
PA14
PA15
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
VSS
VDD18
VDD
VBAT
reserved
PC13
PC14
PC15
PF0
PF1
NRST
VSSA
VDDA
PA0
PA1
PA2
PA3
PC13
PC14
PC15
PF0
PF1
NRST
VSSA
BYPASSREG1
VDDA
PA0
PA1
PA2
PA3
STM32F031
PF7
PF6
PA13
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12
VDD18
OUT1
LVG3
LVG2
LIN3
LIN2
LlN1
V
CC
VDD
VSS
BYPASSREG2
VSSA2
PB11
PB10
PB2
NPOR
VDD
PB1
PB0
PA7
PA6
PA5
PA4
LVG1
FAUL
T
I
OD
OD
SMART
SD
PGND
+5V
CIN
+
-
+
V
REF
UVLO
SGND
VDD
PB1
PB0
PA7
PA6
PA5
PA4
VSS
CIN
OD
DS13048
-
Rev 4
page 3/32
STSPIN32F0251, STSPIN32F0252
Pin description and connection diagram
2
Pin description and connection diagram
Figure 2.
STSPIN32F025x pin connection (TQFP top view)
Figure 3.
STSPIN32F025x pin connection (QFN top view)
DS13048
-
Rev 4
page 4/32
STSPIN32F0251, STSPIN32F0252
Pin description and connection diagram
Table 1.
Legend/abbreviations used in the pin description table
Name
Pin name
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
AO
P
Pin type
S
I
I/O
FT
FTf
TTa
I/O structure
TC
B
RST
Notes
Pin functions
Gate Driver Analog Output
Gate Driver Supply\GND pin
Supply pin
Input-only pin
Input / output pin
5 V-tolerant I/O
5 V-tolerant I/O, FM+ capable
3.3 V-tolerant I/O directly connected to ADC
Standard 3.3V I/O
Dedicated BOOT0 pin
Bidirectional reset pin with embedded weak pull-up
resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate Functions
Additional functions
Functions selected through GPIOx_AFR registers
Functions directly selected/enabled through peripheral
registers
Table 2.
STSPIN32F025x MCU-Driver internal connections
MCU pad
PB12
PB13
PB14
PB15
PA8
PA9
PA10
PA11
-
Type
I/O - FT
I/O - FT
I/O - FT
I/O - FT
I/O - FT
I/O - FTf
I/O - FTf
I/O - FT
Power
controller pad
FAULT
LIN1
LIN2
LIN3
HIN1
HIN2
HIN3
EN
EPAD
Gate Driver Fault output
Gate Driver Low Side input driver 1
Gate Driver Low Side input driver 2
Gate Driver Low Side input driver 3
Gate Driver High Side input driver 1
Gate Driver High Side input driver 2
Gate Driver High Side input driver 3
Gate Driver shut down input
Function
Note:
Each unused GPIO inside the SiP should be configured in OUTPUT mode low level after startup by software
DS13048
-
Rev 4
page 5/32
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