How to use FPGA and RS485 for industrial communication

    Transmitting information in industrial applications can be challenging. In this project, let's see how we can do this using an FPGA and RS485.

    Project Background:

    Many FPGAs are deployed in industrial environments to control processes, drives, actuators, and sensors.

    The protocols used to interface with these sensors, actuators, and drives are very diverse, although time-sensitive networking is changing this. There are many different protocols, such as Modbus, Profibus, and EtherCat. Many of these protocols are based on common physical layers, such as EIA/RS485, EIA/RS422, and Ethernet.

    One of the key requirements for many interfaces is the ability to operate with a low link error rate in the physical layer in a noisy industrial environment. Both EIA/RS485 and EIA/RS422 are differential physical layers that provide a robust multi-point interface capable of bidirectional (EIA/RS485) or unidirectional (EIA/RS422) communication.

    There are many application layer protocols that can be implemented using these physical layers. In this project we will look at connecting two MiniZeds together using the RS485Pmod and a custom application layer protocol.

Hardware Components

Avnet MiniZed × 1

    DigilentPmodRS485×2

    Software Applications and Online Services

AMD-Xilinx Vivado Design Suite

    AMD-Xilinx Vitis unified software platform

    Application Layer

    The custom communication protocol implemented will enable the master MiniZed to read or write 32-bit words from the 16-bit address space within the slave MiniZed. For this project, we will be reading and writing from the BRAM in the slave. However, this BRAM may be populated by sensors collecting data on the MiniZed.

    Data will be sent over the RS485 link using UART, and the data packet contains multiple UART transmissions

    The format for writing is

    《STX》《ADDRMSB》《ADDRLSB》《DataMSB》《Data》《Data》《DataLSB》

    The slave will respond to writes with a single byte ACK or NACK

    The format to read is

    《ENQ》《ADDRMSB》《ADDRLSB》

    The read response from the MiniZed slave will be

    《SOH》《ADDRMSB》《ADDRLSB》《DataMSB》《Data》《Data》《DataLSB》

    SOH, STX, ENQ, ACK, and NACK are defined in the ASCII table

    Of course, this protocol can be implemented using UART in a processor like ZYNQ to make the protocol scalable. I created custom RTL modules for UART, ProtocolMaster and ProtocolSlave.

    Since RS485 is directional on the same twisted pair, the protocol must enable the RS485 transmitter only when it is ready to transmit, to reduce the possibility of contention on the bus when multiple transmitters attempt to transmit at the same time.

    MiniZedMaster

    The MiniZedMaster design will use the PS core to send and receive data over the RS485 interface. This will enable the link to be tested as data should be able to be written over the link and then read back from the block RAM in the MiniZed slave in a different order.

    The design uses an AXIGPIO module connected to the protocol master module to drive the interface requirements of the protocol master module. This includes the address, data, and read or write operation. The result provides the address to read from and the data to read.

    To be able to debug the application I also included several ILAs that help understand the system behavior.

    The software application running on MinizedMaster is

    #include

    #include "platform.h"
#include "xil_printf.h"
#include "xgpio.h"

    #define DATA_ADDR XPAR_GPIO_0_DEVICE_ID
#define VALID_RW  XPAR_GPIO_1_DEVICE_ID
#define DATA_BCK  XPAR_GPIO_2_DEVICE_ID
#define DATA_VALID_CH 1
#define ADDR_RW_CH 2

    XGpio Gpio1;
XGpio Gpio2;
XGpio Gpio3;

    int count = 0;

    int main()
{
 init_platform();

    XGpio_Initialize(&Gpio1, DATA_ADDR);
 XGpio_Initialize(&Gpio2, VALID_RW);
 XGpio_Initialize(&Gpio3, VALID_RW);

    while(1){

    u32 rd_data, rd_addr;
 //write

    XGpio_DiscreteWrite(&Gpio1, DATA_VALID_CH, count );
 XGpio_DiscreteWrite(&Gpio1, ADDR_RW_CH, 0x5001);
 XGpio_DiscreteWrite(&Gpio2, ADDR_RW_CH, 0x0);
 XGpio_DiscreteWrite(&Gpio2, DATA_VALID_CH, 0x1);
 XGpio_DiscreteWrite(&Gpio2, DATA_VALID_CH, 0x0);

    usleep(1000);
 //read
 XGpio_DiscreteWrite(&Gpio1, ADDR_RW_CH, 0x5001);
 XGpio_DiscreteWrite(&Gpio2, ADDR_RW_CH, 0x1);
 XGpio_DiscreteWrite(&Gpio2, DATA_VALID_CH, 0x1);
 XGpio_DiscreteWrite(&Gpio2, DATA_VALID_CH, 0x0);
 usleep(10000);

    rd_data = XGpio_GetDataDirection(&Gpio3, 1);

    rd_data = XGpio_DiscreteRead(&Gpio3, 1);
 rd_addr = XGpio_DiscreteRead(&Gpio3, 2);

    if(rd_data != count){
  printf("read back not correct %d, %d ", rd_data, count);
 }

    usleep(1000000);
 count++;

    }
 cleanup_platform();
 return 0;
}
MiniZedSlave

    The MiniZedSlave uses the PS module to provide the clock to the logic design. The protocol slave is connected to a BRAM which stores the data provided over the communication link.

    This implementation of the MiniZedSlave requires no software, only the ProtocolSlave, UART and BRAM. As with the MiniZedMaster, the PS provides the clock for the module.

    Ordinary XDC

    Both the MiniZedMaster and Slave use Pmod1 on the MiniZed to connect to the RS485Pmod. Therefore, the XDC files for both are identical.

    set_property IOSTANDARD LVCMOS33 [get_ports {re[0]}]

    set_property IOSTANDARD LVCMOS33 [get_ports de]
set_property IOSTANDARD LVCMOS33 [get_ports rx]
set_property IOSTANDARD LVCMOS33 [get_ports tx]
set_property PACKAGE_PIN L15 [get_ports {re[0]}]
set_property PACKAGE_PIN M14 [get_ports de]
set_property PACKAGE_PIN L14 [get_ports rx]
set_property PACKAGE_PIN M15 [get_ports tx]

    Wiring the RS485 bus

    The RS484 bus is pretty simple, but we do need to wire up the Pmod correctly as shown in the Digilent Pmod RS485 Reference Guide.

    Both ends of the RS485 terminals need to be terminated with a resistor, which can be installed or not on the PmodRS485 using a jumper. For this application, two resistors need to be installed.

    When wiring, be careful to wire the loop for the receiver on the Pmod.

    Hardware Testing

    Using a software application running on the MiniZed master, we can read and write to the BRAM memory in the MiniZed slave. However, to understand how this works, we can best learn by looking at the waveform on the bus.

    A write transfer from the host on the logical TX pin looks like this

    The corresponding bus terminal is shown below - note the 0x06 at the end which is the acknowledgement.

    The RX pin on the master indicates writes and write confirmations via a logical RX signal. Both the MiniZedMaster and Slave are designed with RX permanently enabled.

    The data read from the MiniZedSlave is shown below, where the data represents the incrementing count written by the MiniZedMaster.

    In the waveform below, a read request can be observed on the bus side before a read response.

    The timing of TX enable relative to TX data is shown below, note how we disable the TX path when a reply is expected.

    Probing the different TX enables on the MiniZedMaster and Slave shows

    in conclusion

    FPGAs provide a great solution for many industrial applications, this project shows how easy it is to connect different boards and transfer data using common industrial interfaces. In this application the data rate is 1Mb/s, line rates up to 16Mb/s or faster can be achieved!