Design of circuit module of fingerprint identification system based on FPGA

This design uses an FPGA with high integration, low power consumption, and short development cycle to complete this design. With the ASIC that implements the system as the research background, it has strong practical significance and broad market space. Xilinx Spartan 3E series FPGA is used as the core control device. This device adopts 90ns advanced technology, has a maximum capacity of 500,000 gates, can support 32-bit RISC processors, and has 128 Mbit parallel Flash, which is enough to meet the design requirements. This project uses embedded soft cores to implement system management and hardware to implement identification algorithms, ensuring the integrity of system functions and the correctness of identification.

Fingerprint collection module

This design uses Fujitsu's MBF200 fingerprint sensor. The MBF200 hardware block diagram is shown in Figure 6. It adopts SPI mode, so MBF200 and FPGA are only connected through four ports: MISO, MOSI, /S/C/S, and SCLK. /S/C/S is the enable terminal of MBF200, SCLK is the system clock of MBF200. When the fingerprint signal needs to be collected, the FPGA sends a low level to /S/C/S, and the MBF200 starts to work. FPGA sends control commands to MBF200 through MOSI to control the data output mode and transmission mode of MBF200. VDD[3:1] is the digital power input, VDDA[2:1] is the analog power input, VSS[3:1] is the digital ground, VSSA[2:1] is the analog ground, so connect it as shown in the figure. In order to prevent digital signals from interfering with analog signals, they are separated by a 10 ohm resistor. And there are capacitors connected between the digital power input and the corresponding digital ground to absorb non-DC signals. In order to prevent interference between the digital ground and the signal ground, this design uses 0 ohm resistor isolation. A 0 ohm resistor is equivalent to a very narrow current path, which can effectively limit the loop current and suppress noise. Resistors have attenuation effects in all frequency bands (0 ohm resistors also have impedance), which is stronger than magnetic beads.

The MODE[1:0] pin is used to set the interface mode used by MBF200. In this design, set MODE[1:0] to 01 and select the SPI transmission mode. In SPI mode, the three interfaces AIN, ISET, and FEST will not be used, but according to the internal circuit structure of MBF200, it is best to connect a resistor to ground.

Fingerprint data processing module

Since fingerprint data processing involves many algorithms and requires a large amount of calculation, this system embeds a Microblaze soft core on the Spartan-3E development board for data processing. First, the data transmitted from the SPI port is sent to SDRAM for storage. There is 32M of SDRAM, which can store many fingerprint data. When creating a fingerprint database, the system takes out the data from SDRAM, puts it into Microblaze for processing, and then stores the processed fingerprint data information in FLASH to form a fingerprint database. In the comparison mode, the data processed by Microblaze is stored in SDRAM, and then the fingerprint image feature data is extracted from FLASH and SDRAM respectively for comparison, and the comparison results are obtained.

Fingerprint data storage module

The pin connection diagram between trataFlash and FPGA is shown in Figure 7. CE[2:0] is the strataFlash enable signal input port. When only one chip is used, CE[2:1] is grounded and only controlled by CE0. Since in this design, the data transmission D between FPGA and FLASH is multiplexed with the FPGA's control line MISO for MBF200, there is a conflict between fetching data from FLASH and controlling MBF200, and the timing is difficult to control, so this design will give Setting BYTE# high turns off A0 and puts strataFlash in X16 mode. D[7:0] in write mode, transfer control command when writing CUI, in buffer write and programming mode. In read mode, D[7:0] sends CFI, data array and flag data. The status register data will not be transmitted through these 8 bits. VPEN is the lock enable input. When VPEN <VPRNLK, the memory will not allow data or commands to be written.

This system uses xilinx's Spartan 3E series FPGA as the core control chip, collects fingerprint images through Fujitsu's MBF200 fingerprint sensor, uses the SPI interface to transmit to the FPGA for data storage, and uses the embedded MicroBlaze processor to process the fingerprint images. Preprocessing such as grayscale filtering, binarization, binary denoising, and thinning is performed to obtain a clear fingerprint image, and then fingerprint feature points are extracted from the clear fingerprint image and stored in the fingerprint database as a filing template. During fingerprint comparison, the same method is used to obtain a comparison template, and then the comparison template and the archiving template are compared using the fingerprint recognition algorithm to obtain the comparison result. This project uses embedded soft cores to implement system management and hardware to implement identification algorithms, ensuring the integrity of system functions and the correctness of identification. This identification system can be used in many aspects such as access control, attendance, and document management, and has a wide range of application prospects.