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Vivado generates IP core issues [Copy link]

Vivado has a big project with a bunch of subroutines. When I generate the IP core, only the top-level IP core is generated, and the IP cores of the subroutines below are not generated. Why is this?

This post is from FPGA/CPLD

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Write the reference call interface function of the ip core into the subroutine, and the ip core will automatically update to the subroutine directory.  Details Published on 2018-8-2 09:30
 

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Write the reference call interface function of the ip core into the subroutine, and the ip core will automatically update to the subroutine directory.
This post is from FPGA/CPLD
 
 

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