DDS signal generator principle and vivado simulation

1. Introduction to DDS

The DDS signal generator uses direct digital synthesis (DDS) technology to improve the frequency stability and accuracy of the signal generator to the same level as the reference frequency, and can perform fine frequency adjustment in a wide frequency range. The signal source designed using this method can work in a modulation state, adjust the output level, and output various waveforms.

2. Principle

The theoretical basis of DDS signal generation is the "Nyquist sampling theorem". The theorem shows that when the sampling frequency is greater than or equal to twice the highest frequency of the analog signal, the original analog signal can be recovered from the discrete sequence distortion-free signal. The principle of DDS signal generation is to sample the analog signal. When a sampling process has occurred and the sampled value has been quantized, the original analog signal is reconstructed from the quantized value. The basic DDS structure is mainly composed of a phase accumulator, a waveform quantization data storage, and a D/A converter. Among them, the phase accumulator and the waveform quantization data storage are called digitally controlled oscillators, which are the digital parts of the DDS structure. The basic structure principle of DDS is shown in the figure below.

In the figure, the phase accumulator is composed of an N-bit adder and an N-bit accumulation register, which is an extremely important part of the DDS module. Driven by the reference frequency clock, the DDS module starts to work; when each reference clock comes, the accumulator accumulates the frequency control word FW and the value output by the register, and inputs the result of the addition into the register, and the accumulation register transmits the data generated when the previous reference clock acts to the accumulator by feedback. In this way, under the action of the clock, the frequency control word can be accumulated continuously. At this time, the data output by the phase accumulator is used as the address to search the amplitude table corresponding to the address in the waveform memory to complete the conversion from phase to amplitude. In the DDS module, the formula for the output frequency is:

It can be seen from the above formula that when the reference signal and the number of bits of the accumulator are given, the final output frequency of the signal is mainly determined by the frequency control word. Therefore, when the frequency control word changes, the output frequency also changes, thereby realizing the basic function of frequency modulation.

3. DDS code

module DDS(

  input clk,

  input rst_n,

  input [31:0]fword,

  input [10:0]pword,

  output [11:0]DA

);

  reg [31:0] r_fword;

  reg [11:0] r_pword;

  reg [31:0] cnt;

  wire [11:0] rom_addr;

  always@(posedge clk or negedge rst_n)begin

    if(!rst_n) begin

      r_fword <= 0;

  r_pword <= 0;

      end

    else begin

      r_fword <= fword;

  r_pword <= pword;

end

  end

  always@(posedge clk or negedge rst_n)

     if(!rst_n)

    cnt <= 32'd0;

   else

    cnt <= cnt +r_fword;

assign rom_addr = cnt[31:20] + r_pword;

blk_mem_gen_0 blk_mem_gen_1 (

  .clka(clk),    // input wire clka

  .addra(rom_addr),  // input wire [11 : 0] addra

  .douta(DA) // output wire [11 : 0] douta

);

endmodule 

The blk_mem_gen_0 instantiation module is the "rom" IP core called in vivado, and the settings are shown in the following two figures.

        The initialization coe file of ROM can be generated by waveform data generator or MATLAB, saved in the project directory, and the initialization file is selected as the generated coe file in ROM.

4. Test Files

`timescale 1ns/1ns

module DDS_tb;

      reg clk;

reg rst_n;

reg [31:0] fword;

reg [10:0] pword;

wire [11:0] YES;

DDS DDS0 (

  .clk   (clk),

  .rst_n (rst_n),

  .fword (fword),

  .pword (pword),

  .YES YES)    

);

initial clk = 1;

always #5 clk = ~clk;

initial begin

   rst_n = 0;

fword = 42955;

pword = 256;

#201;

rst_n = 1;

end

endmodule 

5. Simulation Results

        In Vivado, click Run Simulation-Run Behavioral Simulation, select DA, and set it to simulate the signal, as shown in the figure below.

Click on the top to run

        In the test file, the input clock is set to 100M, the frequency control word is 42955, and the phase control word is 256. The frequency calculated by the above output frequency calculation formula is =42955x100000000/2^32=1000.12Hz, and the period is 1ms. The waveform is measured and the period is about 1ms, as shown in the figure below.

6. Conclusion

        The simulation results are consistent with the expected effect, proving that the module is correct. Interested readers can add the DAC module and low-pass filter module to the above part to get a DDS signal generator.