DFT design/digital backend PR/digital backend integration/system software/and other positions, Beijing/Shanghai/Nanjing

许许小猎

DFT design/digital backend PR/digital backend integration/system software/and other positions, Beijing/Shanghai/Nanjing [Copy link]

We are sincerely recruiting IC design engineers. Interested parties can send their resumes to shuyan.xu@risfond.com, or contact Ms. Xu at 16622901990.

DFT

job description

1. Participate in the definition, design and implementation of DFT architecture of AI core and SOC; 2. Participate in the development of hierarchical scan insertion flow, EDT insertion flow, ATPG flow; 3. Participate in the development of hierarchical memory BIST insertion flow, diagnosis flow, repair flow; 4. Participate in the design of customized macro BIST RTL design and verification; 5. Responsible for chip test pattern generation, ATE debug, yield analysis;

Job Requirements

1. Have comprehensive DFT design knowledge and experience; 2. Be familiar with at least one of Mentor or Synopsys' DFT flow; 3. Have solid Verilog/SystemVerilog code writing ability; 4. Be proficient in the use of synthesis, STA, Formality tool; 5. Have strong VCS simulation waveform debugging ability;

bonus:

1. Experience in at least 3 SOC design and tape-outs; 2. DFT design experience for AI chips is preferred; 4. Familiar with scripting languages, such as Perl, Python or Tcl; 5. Good communication skills and teamwork spirit.

Backend PR

job description

1. Implement SOC chip netlist to GDS backend, responsible for full chip floorplan, powerplan and subsequent PR process; 2. Create and maintain chip level and block level PR flow;

Job Requirements

1. 5 years of relevant work experience, with good self-motivation and entrepreneurial mentality; 2. Familiar with 28/16nm or below processes, familiar with low power design of multiple power domains, and experience in back-end implementation and successful tapeout of more than 2 large SOC chip level; 3. Good communication and cooperation skills; 4. Good scripting skills; Bonus points: (one or more of the following) 1. Experience in chip level timing signoff or physical signoff; 2. Experience in power analysis, familiar with UPF/CPF; 3. Experience in ARM CPU implementation; 4. Experience in back-end implementation of high-speed interface circuits, including MIPI, DDR/LPDDR.

Backend Comprehensive

job description

1. Responsible for the SDC structure design of chip and block, and collaborate with RTL Designer to complete SDC creation and maintenance; 2. Responsible for the establishment and optimization of Synthesis/Formal check/lowpower check and other flows; 3. Responsible for the chip level timing signoff of SOC chip, and cooperate with PR engineers to complete timing analysis and convergence; 4. Assist in completing DFT related work;

Job Requirements

1. More than 5 years of relevant work experience, with good self-driving power and entrepreneurial mentality; 2. Proficient in Synthesis/Formal/STA tools and processes; 3. Familiar with 28/16nm or below processes, familiar with low power design, able to create and maintain CPF/UPF, and participated in the synthesis and formal check of more than 2 SOCs; 4. Good communication and cooperation skills; 5. Good scripting skills; Bonus points: (one or more of the following) 1. Chip or block PR experience; 2. Power analysis experience;

system software

job description

1. Design, development and debugging of the underlying system software of AI SoC submodules; 2. Design, development and debugging of the HAL layer; 3. Design, development and debugging of the kernel module; 4. Writing of test cases, design documents, etc.;

Job Requirements

1. More than 3 years of Linux driver development experience, familiar with the Linux kernel, and master basic driver development skills; 2. Familiar with ARM/Risc-V architecture, various bus protocols (including but not limited to I2C/SPI/Uart/PCIe); 3. Familiar with Linux C/C++/assembly programming; 4. Familiar with various debugging tools and able to quickly locate problems; Bonus points 1. Relevant experience in RTOS, QNX, etc.; 2. In-depth understanding of a subsystem;