14-bit 125MSPS quad-channel ADC circuit diagram (enhanced SNR performance through back-end digital summation)

　　Circuit functions and advantages

The circuit shown in Figure 1 is a simplified diagram of a 14-bit, 125 MSPS quad ADC system that uses back-end digital summation to improve the signal-to-noise ratio (SNR) from 74 dBFS for a single-channel ADC to 78.5 dBFS for a quad-channel ADC. This technology is particularly suitable for applications requiring high SNR, such as ultrasound and radar, and takes advantage of modern high-performance, low-power, quad-channel pipelined ADCs.

This circuit uses the basic principle that uncorrelated noise sources are summed on a root sum of squares (rss) basis, while signal voltages are summed on a linear basis.

Figure 1. Basic block diagram of summing four parallel ADCs for higher SNR.

　　Circuit description

The input to each ADC consists of a signal term (VS) and a noise term (VN). Summing the four noise voltage sources gives the total voltage VT, which is the linear sum of the four signal voltages plus the roots of the square sums of the four noise voltages, for example:

Since VS1 = VS2 = VS3 = VS4, the signal is effectively multiplied by 4, while the converter noise - which has an equivalent rms value - is only multiplied by 2, so the signal-to-noise ratio increases by a factor of 2, or 6.02 dB. Therefore, the 6.02 dB SNR increase is the result of one additional bit of effective resolution resulting from summing four similar signals. Since SNR (dB) = 6.02N + 1.76 dB, where N is the number of bits, thus

Table 1 shows the theoretical SNR value obtained by summing the outputs of multiple ADCs. For convenience, one should obviously choose to sum the four ADCs. Certain critical situations may require more ADC summing, but this depends on other system specifications (including cost) and available board space.

Table 1. Relationship between increasing SNR and number of ADCs Number of ADCs SNR increase (dB)

The ideal SNR for a 14-bit ADC is (6.02 &TImes 14) + 1.76 = 86.04 dB The AD9253 datasheet specifies a typical SNR of 74 dB, but it produces an ENOB of 12 bits.

The circuit shown in Figure 1 integrates a passive receiver front end and consists of four analog input channels. The device used is the 14-bit, 125 MSPS four-channel analog-to-digital converter AD9253.

This circuit accepts a single-ended input and converts the input to a differential signal through two wide-bandwidth (3GHz) M/A-COM ETC1-1-13 baluns with an impedance ratio of 1:1 in a double-balanced configuration, as shown in Figure 2 Show.

Figure 2. Input simulation summation network

All four ADC inputs are connected on the secondary side of the balun configuration. There is no gain in the circuit, and each analog input pair has a simple filtering function to reduce residual kickback signals that may be fed back to adjacent ADC channels.