[Analysis of the topic of the college electronic competition] - 2016 Shanghai TI Cup B "Design of short-wave frequency digital communication system"

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[Analysis of the topic of the college electronic competition] - 2016 Shanghai TI Cup B "Design of short-wave frequency digital communication system" [Copy link]

 

1. Mission

Design a shortwave band all-digital transceiver communication demonstration system, requiring the communication modulation mode to adopt BPSK modulation, the modulation symbol rate to be fixed, the modulation carrier to be set by the program, the range is 1MHz ~ 5MHz , and the modulated carrier to be removed at the receiving end, and the baseband waveform to be observed with an oscilloscope. The following figure shows the design block diagram of the demonstration system:

II. Requirements

1. Basic requirements

( 1 ) Generate three data sequences: all -1 sequence, 01 alternating sequence, and pseudo-random periodic sequence (generator: f ( x ) = x ⁴ + x +1 );

( 2 ) Perform BPSK modulation on the data sequence , and set the modulation symbol rate to 25K ;

( 3 ) The modulation carrier is set to 2.5MHz ;

( 4 ) The output amplitude of the modulation signal is 5Vpp ;

( 5 ) The receiving module realizes carrier synchronization, recovers the baseband, and observes the baseband waveform with an oscilloscope.

2. Development part

( 1 ) The modulated carrier of the transmitter module is set in the range of 1MHz to 5MHz with a step of 1KHz ;

( 2 ) The receiving module automatically searches and tracks within the frequency range, realizes carrier synchronization, and restores the baseband. The baseband waveform can be clearly observed using an oscilloscope;

( 3 ) Change the signal output amplitude of the transmitting module to 0.1V~5Vpp , and the receiving module can achieve correct reception;

( 4 ) Friendly human-computer interaction, with parameter setting function, carrier frequency and other status information display functions.

3. Description

( 1 ) Basic parts 1 to 4 are required to be implemented in the transmitter module;

( 2 ) The carrier in the transceiver module is generated by itself and cannot be replaced by a signal source;

( 3 ) The transmitting module and receiving module are designed independently, and the transmitting and receiving modules are connected by wire, and the same reference clock cannot be selected;

( 4 ) Provide test points for receiving and sending signals at each node (such as data sequence, baseband forming, receiving and sending local carrier, and modulation and demodulation signals, etc.), which can be observed with an oscilloscope or spectrum analyzer to conduct functional and performance tests.

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Question analysis and design

There are many modules related to this topic, which will be analyzed one by one below.

1. Sequence generator.

Generate three sequences according to the requirements of the question: all -1 sequence, 01 alternating sequence, and pseudo-random periodic sequence (generator: f ( x ) = x ⁴ + x +1 ). The all- 1 series is actually a constant logic high level; the 01 alternating series is actually a clock signal; the circuit of the pseudo-random sequence generator is as shown below.

The symbol rate of BPSK is the same as the clock of the shift register, which is 25kHz as required by the question .

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2. Baseband forming circuit.

First, encode the digital sequence. Since the digital sequence required by the question contains a sequence of all 1s , this encoding is necessary, otherwise the receiver will not be able to restore the synchronization signal. In addition, a basic feature of all PSK signals is that their demodulation has phase ambiguity, so this encoding must use a relative code format, the most common of which is the differential Manchester code.

The encoding rules of differential Manchester code are as follows: each code element in the baseband bit stream is split into two pulses, and a level jump occurs at the midpoint of each code element; " 1 " has a level jump at the midpoint of the code element and at the beginning of the code element, while " 0 " only has a level jump at the midpoint of the code element. Since 1 and 0 are only related to the level jump of the signal and have nothing to do with the absolute level, phase ambiguity is avoided. The figure below is the waveform of differential Manchester code:

When using differential Manchester code, the clock of the encoding circuit should be twice the clock of the sequence generator ( 50kHz in this question ) and the two clocks should be phase-related. The simplest way is to design a 50kHz clock generator (for example, using a 555 chip) as the clock of the encoder, and divide this clock by 2 as the clock of the sequence generator.

A premodulation filter should be inserted after the encoder. This filter is a low-pass filter with a flat delay characteristic, which can effectively suppress the out-of-band power radiation caused by the high-order harmonics of the rectangular pulse signal.

The structure of the sequence generator and baseband shaping circuit is shown in the figure below. The low-pass filter is a 2nd -order Bessel-type active filter, designed with a cutoff frequency of 65kHz and a Q value of 0.58 . The rest of the circuits are digital logic circuits and will not be expanded here.

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3. Local carrier generator.

According to the requirements of the development part of the question, the carrier frequency is set in 1MHz ~ 5MHz with 1KHz steps. Obviously, the frequency synthesizer composed of a phase-locked loop is the most suitable choice. Considering that the frequency is not high, the specific circuit selection is simpler with MC145151 as the phase detector and frequency divider plus the VCO in HC4046 . The circuit is shown in the figure below. Among them, R1 , R2 , C1 , C2 form a loop filter, R3 , R4 and C3 are the bias resistor and oscillation capacitor of the VCO , which determine the oscillation frequency of the VCO .

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4. BPSK modulator and signal filtering and amplification .

The expression of BPSK modulated wave is:

Where V _c sin( ω _c t ) is the carrier, a ( t ) is the bipolar baseband signal. For a rectangular wave, a ( t ) = +1 or -1 . For the baseband signal after the premodulation filter, the DC component is filtered out by AC (capacitor) coupling, which is the bipolar baseband signal a ( t ) . Multiplying the bipolar baseband signal a ( t ) with the carrier can get the BPSK modulated wave.

The specific circuit is analyzed below.

In principle, any device with multiplication function can be used as a BPSK modulator, such as the common modulation and demodulation chip MC1496 or multiplier chip AD835 in the laboratory , and even a diode or transistor can be used as a modulator. However, in the actual circuit, more problems must be considered, such as the level matching problem of the front and back stages, the power supply compatibility problem, the difficulty of design and production, whether the components are easy to obtain, etc. Among the aforementioned multiplication devices, it is obvious that the design of diodes or transistors is relatively complicated (maybe the circuit is very simple, but the performance parameter calculation is complicated, and the distortion is also difficult to control). After comparing the other two integrated circuits, it can be found that although MC1496 can meet the modulation requirements, its power supply is difficult to unify with other chips in the system, there are more peripheral devices, and there are more things to consider in the design. AD835 is relatively simple, its power supply is ±5V (compatible with the op amp in the system), the gain is fixed, and there are almost no peripheral devices, so it is the first choice for this design.

One thing to note when choosing AD835 is that its input differential voltage range is ±1V and common mode voltage range is -2.5V~+3V . Of the two input signals at this stage, one is the baseband signal and the other is the carrier signal output by the frequency synthesizer. They are both digital circuit signals with peak-to-peak values close to 5V (assuming that the DC gain of the low-pass filter following the baseband signal is 1 ), which exceeds the allowable input voltage range of AD835 . Therefore, a resistor divider is required at the input end.

The figure below is a modulator circuit based on AD835 . The amplifier behind it is to meet the requirements of the question: the output voltage of the transmitter module is 0.1Vpp~5Vpp . Since the carrier frequency varies in the range of 1MHz to 5MHz , this is a high-frequency broadband amplifier. The selection of a high-speed operational amplifier (such as AD8047 or OPA695 ) can meet the requirements. The specific amplification factor should be determined according to the output amplitude of the modulator.

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6. Signal reception and conditioning.

This is a high-frequency broadband amplifier with a bandwidth of 1MHz to 5MHz . Since it is required to be able to achieve correct reception within the range of 0.1Vpp~5Vpp , this amplifier should have an AGC function, and the AGC control range should not be less than 34dB . There are multiple VGA chips that can be used to design this AGC amplifier. For example , AD603 has a variable gain range of about 40dB , and the gain and bandwidth can be adjusted through an external feedback resistor. When the external feedback resistor is short-circuited, the gain is about -10dB~30dB , and the bandwidth is 90MHz .

The AGC amplifier circuit designed based on AD603 is shown in the figure below. Since the question requires the maximum output voltage of the transmitter module to be 5Vpp , and the maximum allowable input voltage of AD603 is only 2V , a 200Ω resistor is connected in series at the input end of the amplifier . This resistor and the input resistance of AD603 100Ω form a voltage divider, so that the actual input voltage of AD603 does not exceed the limit, and at the same time, the output amplifier of the transmitter module is not overloaded.

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The most difficult part of AGC circuit design is how to obtain accurate AGC control voltage. The circuit in the figure above uses two transistors and capacitor C to form an AGC control voltage generation circuit. Its working principle is as follows:

The control voltage of AD603 is the difference between the potential of pin 1 and the potential of pin 2. When it changes between -0.5V and +0.5V , the gain changes from the minimum value to the maximum value, that is, the range of the control voltage is 1V . The potential of pin 2 is fixed at 1V by the resistor divider , and the potential of pin 1 is the voltage on capacitor C , so the control voltage range on capacitor C is 0.5V~1.5V .

Transistor Q1 forms a constant current source to charge capacitor C. If there is no Q2 , the voltage on capacitor C will eventually reach more than +2V . When the negative voltage peak of the amplifier output is lower than -0.7V ( Q2 's emitter junction voltage drop), Q2 will be turned on, capacitor C will discharge through Q2 , and the voltage will drop. When the discharge current flowing through Q2 is balanced with the charging current flowing through Q1 , the voltage on capacitor C determines the gain of the amplifier. Since the charging current of Q1 is constant, the discharge current after reaching balance is basically unchanged, that is, the output voltage of the amplifier is basically unchanged, achieving the purpose of AGC .

To calculate the output voltage, we need to calculate the capacitor charging current and discharging current when the capacitor reaches equilibrium. For the circuit in the figure above, the charging current flowing through Q1 is

Where 2 is the voltage difference between the power supply +5V and the base of Q1 , and 0.7 is the voltage drop across the emitter junction of the transistor .

However, the discharge current flowing through Q2 is a pulse waveform with periodic amplitude changes, which is not easy to calculate accurately. Assuming the output voltage peak value is V _p , an approximate result is

其中

By making the above two currents equal, we can get the peak value Vp of the output voltage _. However , this is a transcendental equation and cannot be solved. We can only get an approximate solution using numerical methods. During debugging, we can adjust the output voltage by changing the ratio of R2 to R1 . The larger the R2/R1, the higher the output voltage. However, considering that the latter stage of this amplifier is a multiplier, and the maximum allowable input voltage of the multiplier is not very high (for example, the maximum input differential voltage of AD835 is ±1V ), it is not advisable to adjust the output voltage too high.

The resistance values of R1 and R2 are determined according to the following principles: The maximum output drive capability of AD603 is 50mA , but the designed output current should be much smaller than this value, so the value of R2 should be roughly between several hundred ohms and 1 kiloohm. R1 should be of the same order of magnitude.

The current flowing through capacitor C fluctuates, and the fluctuation period is the period of the input baseband signal. The fluctuation amount can be calculated as half of the charging current I1 calculated previously. This current fluctuation will cause the AGC control voltage to fluctuate, and further _cause the gain to fluctuate. The control voltage fluctuation amount is

Where T is the period of the input baseband signal, i.e. 1/50kHz . The gain fluctuation is , where k is the gain control coefficient of AD603 , which is about 40dB/V . Therefore, as long as an allowable gain fluctuation is determined, such as 1dB , the size of C can be deduced from the above relationship .

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7. Carrier recovery and BPSK demodulation.

This part of the circuit is required to be able to automatically search for the input signal frequency in the range of 1MHz to 5MHz and achieve synchronization.

To demodulate the PSK signal, a carrier synchronization signal is required. Since the question clearly states that the same reference clock cannot be used between the transceiver modules, the carrier synchronization signal must be restored in the receiving module.

The BPSK signal is

The baseband signal a ( t ) is +1 or -1 . Usually, the probability of +1 and -1 appearing in the baseband signal is almost the same (including the differential Manchester encoding used in this question), that is, the average component of the baseband signal is 0. At this time, there is no carrier frequency component in the BPSK modulated wave, and the carrier frequency synchronization signal of the BPSK signal cannot be directly locked by the phase-locked loop.

There are two types of BPSK synchronous demodulation circuits, one of which is called a square ring, and the circuit structure is shown in the figure below.

This circuit first squares the BPSK modulated wave:

The baseband signal a ( t ) is equal to +1 or -1 . After being squared, an average DC component appears. Therefore, the squared signal contains twice the frequency of the carrier signal . The phase-locked loop is used to lock this twice -frequency signal, and then the output of the phase-locked loop is divided by 2 to obtain the carrier synchronization signal. The divided synchronization signal may have the same phase as the transmitter, but it may also be 180 ° different from the transmitter (opposite phase), which is phase ambiguity. This is why the transmitter uses differential Manchester code.

The phase-locked loop in this circuit is designed according to the requirements of the usual synchronous circuit, and its closed-loop bandwidth should be much smaller than the input frequency. The synchronous demodulation circuit is a multiplier. After the input signal is multiplied by the synchronous signal, the low-frequency part output by the filter is the baseband signal. Therefore, the order and cutoff frequency of this low-pass filter should ensure that the baseband signal passes and the carrier signal is sufficiently attenuated. The specific details will not be discussed in detail.

The question requires that the baseband signal be sent to an oscilloscope for observation. The result should be similar to the figure below, which is usually called an "eye diagram".

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discuss

This problem is a very typical digital communication system. If an up-conversion circuit is added to the transmitting module to increase the carrier to the transmitting frequency, and then the carrier is sent to the antenna for transmission after the RF power amplification, and RF preamplification, down-conversion, and intermediate frequency amplifier are added to the receiving module, and a bit synchronization circuit and decision output are added after the baseband output, it is basically a complete wireless digital communication system.

hunterswift

It looks great!

tonyhy1976

The competition topics are quite deep, so study more.

zhaoyuyan

mwangwdwa

Knowledge never goes out of date, come on!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!