LTC2325

xkl5599 · Published on 2021-11-30 19:36

LTC2325 [Copy link]

According to your previous post, the sync signal is input at 10MHz, output at 10MHz, and then the phase and duty cycle are multiplied by 2. It seems that there is a big error. I don't know if my configuration is correct.

littleshrimp · Published on 2021-11-30 19:54

xkl5599 · Published on 2021-12-14 14:06

This post was last edited by xkl5599 on 2021-12-1 08:49

littleshrimp posted on 2021-11-30 19:54

What function does the sync_5_0 IP have?

littleshrimp

xkl5599 posted on 2021-12-1 08:48 littleshrimp posted on 2021-11-30 19:54 What does this sync_5_0 IP achieve...

This module is relatively simple and mainly implements the following functions.

xkl5599

This post was last edited by xkl5599 on 2021-12-1 14:10

littleshrimp published on 2021-12-1 11:50 This module is relatively simple and mainly implements the following functions.

I am a little confused about the terms sync and sync_out. Does sync generate sync_out or does sync_out generate sync?

littleshrimp

xkl5599 posted on 2021-12-1 14:08 littleshrimp posted on 2021-12-1 11:50 This module is relatively simple and mainly implements the following functions. This syn ...

Because it has been a long time, I forgot how the module was implemented, so I wrote a simulation file to see the result. The timing is the result of the bottom picture. Inputting a 10MHz signal will output the same timing as sync_out.

xkl5599

This post was last edited by xkl5599 on 2021-12-1 16:21

littleshrimp posted on 2021-12-1 14:49 Because it has been a long time, I forgot how the module was implemented at that time, so I wrote another simulation file to see the results. The timing is the one at the bottom...

First, the 110M clock PLL generates a 10MHz clock, right? Then 10MHz is used as input to generate clk_out_10_sync

, then clk_out_10_sync is used as input and then output sync

This is the order, right?

littleshrimp

xkl5599 posted on 2021-12-1 16:19 littleshrimp posted on 2021-12-1 14:49 Because it has been a long time, I forgot how the module was implemented at that time, so I wrote another simulation...

right

xkl5599

littleshrimp posted on 2021-12-1 17:24 Yes

Thanks, finally got the data.

littleshrimp

xkl5599 posted on 2021-12-2 16:40 Thanks, I finally have the data

Congratulations

xkl5599 · Published on 2021-12-14 14:06

xkl5599 posted on 2021-12-1 08:48 littleshrimp posted on 2021-11-30 19:54 What does this sync_5_0 IP achieve...

You said it was generated by 10M clock, but your timing diagram is obviously not 10M.

Your cycle is 5ns

hlbht2000

Study

13077

Is there an official code for LTC2325-12?

13077

Please tell me how the timing of DATA_VALID is generated

xkl5599

13077 Published on 2022-6-21 14:02 Is there an official code for LTC2325-12?

have

13077

13077 Published on 2022-6-21 14:02 Is there an official code for LTC2325-12?

Is it enough to cut off the 12-digit official code of LTC2325-16?

13077

13077 Posted on 2022-6-23 12:33 Please tell me how the timing of DATA_VALID is generated

xkl5599

13077 Published on 2022-6-24 11:09 Is it enough to cut 12 digits of the official code of LTC2325-16?

You can try

13077

This post was last edited by 13077 on 2022-6-28 00:38

xkl5599 posted on 2022-6-27 08:44 You can try

Please tell me why the output is ffff

xkl5599

13077 posted on 2022-6-27 13:36 xkl5599 posted on 2022-6-27 08:44 You can try it. Please tell me why the output is ffff

Is the signal correct?

LTC2325 [Copy link]

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