Successfully used ZYNQ to drive LTC2325-16

littleshrimp

Successfully used ZYNQ to drive LTC2325-16 [Copy link]

 

I have been working on ZYNQ (mining board) driving LTC2325-16 ADC these days . I feel that FPGA is too difficult. For a novice like me, it is not like a microcontroller that can "easily" use trial and error to complete the desired function by constantly modifying the code. This is really too time-consuming. These days, I basically listen to the whirring of the CPU fan. The electricity bill has increased, I have less sleep, and I have lost a lot of hair. However, after a few days of learning, many compilation errors can be easily solved.

LTC2325-16 is a 4- channel 16- bit 5MSPS ADC that supports serial LVDS output. The timing does not seem complicated. I drew and soldered the board myself. I used a low-quality 1117 and burned the power chip before, so I am not sure if it is good. The differential pairs of the mining board do not appear in pairs and the connection with LTC2325-16 needs to be converted through the cable. Once there is a problem, there may be problems everywhere.

At first, it felt very easy to read the ADC data, but it was unstable and often contained erroneous data. After a few days of debugging, I found that one of the LVDS clock lines was not crimped properly. The LTC2325-16 could read the clock, but it often made mistakes. Because the clock was 100MHz and the oscilloscope I had only had a bandwidth of 100MHz , it was difficult to see the data. At the beginning, when I measured, I found that the n line of the clock had no output, and I thought that the FPGA was not configured properly. Because I was not familiar with FPGA , I always suspected that the code was not written well. After various changes to the code, I finally found that the data line was broken.

After the data line was connected, the data read was a little better, but still abnormal. In the following days, I basically worked on the timing of LTC2325-16 . The timing looked relatively simple (I thought it was simple). I did not use the official Verilog , because that code was from Altera , and there were some chip-related codes so I wrote it myself.

Because I couldn't measure the actual output timing of the FPGA , I wasn't sure what was wrong with the waveform that looked perfect. I had no choice but to use the official code and study the part related to Altera , which was mainly the code of a clock PLL , with a 110MHz input , 2 55MHz , 2 110MHz , a 220MHz , and a 5MHz output . The 5MHz , 55MHz , and 110MHz all had phase shifts. I started to work on it yesterday. After understanding it, I thought it was okay, but I found that I couldn't work it out with ZYNQ . The reason was that the clock wizard in Vivado couldn't configure the output of a 5MHz clock with a phase shift of 1.62 degrees and a 4% duty cycle. The duty cycle can't be less than 40% .

After continuous testing, we found that if the input is 10MHz and the output is also 10MHz , the configuration can be very flexible. We just need to multiply the phase and duty cycle by 2 , and then write a code to set the odd level of the 10MHz output clock to 0. The function can finally be realized. The final clock tree looks like the following.

The clock problem has been solved. What remains is to modify the code and send the data to the PS end through AXI-FULL . The ADC settings use AXI-LITE to configure the PS . After the modification, I tested the data and was quite satisfied.

Because data transmission from PS to PC has not been implemented , the waveform display of the computer is realized through JTAG . Xilinx SDK can output memory data through XSCT , and the data can be output to the window by adding address and length through mrd .

Copy the output data, sort it out through EXCEL , and then convert the hexadecimal to decimal to see the waveform. I did this at first, but later found it troublesome, so I used the host computer to receive the pasted data and sort it out through code. This is much more convenient. Basically, you can see the waveform by outputting, copying, and pasting. Later, I found that copying is also troublesome because the data is very long and needs to be copied from the beginning to the end. Finally, use mrd -bin -file D:/ mem.bin 0x100 1000 to output the memory data to the file. The host computer clicks a button and automatically reads the ADC data in this file, which is more convenient.

Because I haven't had a signal generator yet, I can only take a simple look at whether the collected data has a lot of noise. I bought one two days ago but it hasn't arrived yet. I will continue after the device arrives.

d1023

What a coincidence! I was just looking for someone to help me make a ZYNQ driver for LTC2325-16, and I found this post on Google.

How can I contact you? Can we try to communicate? I am in Shenzhen

littleshrimp

d1023 posted on 2020-12-20 22:54 What a coincidence, I was just looking for someone to help me make ZYNQ driver LTC2325-16, and I found this post on Google. How can I contact...

Hello, I am a novice in FPGA and I may not be able to meet your requirements.

LTC2325-16 officially provides CPLD Verilog code

DC2395A_CPLD_Source_Code.zip (256.59 KB, downloads: 64)

2020-12-21 10:56 上传

点击文件名下载附件

You can find someone who develops FPGA and move it to ZYNQ.

It should be easy for an experienced person

d1023

littleshrimp posted on 2020-12-21 10:57 Hello, I am a novice in FPGA and I think it can't meet your requirements. LTC2325-16 officially provides the Verilog code of CPLD. You can find someone to open...

Thanks

奔向太平洋

Can you please send me a screenshot of the complete block design?

littleshrimp

Running to the Pacific Ocean published on 2022-2-22 23:34 Can you please send me a screenshot of the complete block design?

I built 2 BDs, one for the LTC2325-16.

The other one is ZYNQ. Since it is my first time to work with FPGA, there are still many unreasonable parts in the writing of this thing. The AXI and network parts all refer to or use the corresponding projects of Heijin.

Fred_1977

I want to ask the original poster, should I build the library for this ADC myself, or call it in EDA? I am also learning FPGA, so I want to learn it.

littleshrimp

Fred_1977 posted on 2022-2-24 14:06 I would like to ask the original poster, should I build the library for this ADC myself, or call it in EDA? I am also learning FPGA, so I will learn from it.

https://www.analog.com/cn/design-center/packaging-quality-symbols-footprints/symbols-and-footprints/LTC2325-16.html

33566

Hello blogger, can you please send me the schematic diagram?

littleshrimp

33566 Published on 2022-3-26 21:28 Hello blogger, can you please send me the schematic diagram? Sorry to bother you

The official evaluation board I refer to for the schematic diagram, with the CPLD and ADC driver removed

33566

littleshrimp posted on 2022-3-26 23:48 The schematic diagram is the official evaluation board I refer to, with the CPLD and ADC driver removed

Hello, blogger! I have a question for you. The signal reference book of LTC2325-16 CLKOUT pin says that it is a delay of SCK signal. So how is this signal generated? Can I understand that after generating SCK, the ADC chip will automatically delay for a period of time and then output it to FPGA at CLKOUT pin? Excuse me.

littleshrimp

33566 Published on 2022-3-28 11:14 Hello blogger! I have a question for you, which is the LTC2325-16 CLKOUT pin. The signal reference book of this pin says it is the SCK signal...

I understand that CLKOUT is used to facilitate reading data in DDR mode. In SDR mode, if the rising edge updates the data, it can be read on the falling edge. If the DDR rising and falling edges update the data, there needs to be a delay to read the data when the data is stable.

33566

littleshrimp posted on 2022-3-28 11:34 I understand that CLKOUT is used to facilitate reading data in DDR mode. In SDR mode, if the rising edge updates the data, it can be read on the falling edge. DDR ...

When programming, CLKOUT is an input signal, so how is this signal generated? How do we configure this pin when programming? Or is the signal on this pin automatically generated by the LTC2325 chip, and we just need to hand it over to the FPGA. Thanks for the blogger's answer, my level is not good enough, please trouble the blogger

littleshrimp

33566 Published on 2022-3-28 15:58 When programming, CLKOUT belongs to the input signal, so how is this signal generated? So how do we configure this pin when programming...

CLKOUT is the clock that ADC outputs to FPGA for reading data. FPGA can use it as input clock to read data.

It seems that this clock is not used in the official routines. The corresponding clock is generated by the FPGA itself, so it can be left floating.

13077

I would like to ask how to generate the DATA_VALID signal timing of the 2325 IP? Is data the data output?

13077

littleshrimp posted on 2022-3-28 16:32 CLKOUT is the clock output by ADC to FPGA for reading data. FPGA uses it as input clock to read data. The official routines...

How to test the reliability of AD?

littleshrimp

13077 Published on 2022-7-6 19:15 Please tell me how to test the reliability of AD

What do you mean by reliability?

13077

Data accuracy, why is it useless to connect the input signal given by the signal generator?

littleshrimp

Input a fixed voltage such as 0 or full scale to see if the data is the same as expected, and then compare it with the data from the signal generator. ILA can directly display the waveform of the corresponding channel.

13077

The manual requires a conversion time of 170ns. Is the clock in the example program too fast?