The entire process of R&D and production of a chip

火辣西米秀

The entire process of R&D and production of a chip [Copy link]

1. Basic process of chip

R&D The design and development of a chip, first of all, is to design the application system according to the needs of the product application, to preliminarily determine the application requirements for chip functions and performance indicators, as well as which functions can be integrated and which functions can only be realized externally, the choice of chip process and process platform, the number of chip pins, packaging form, etc., to achieve low cost and high performance of the entire application system and achieve the best cost performance.
2. After that, enter the system development and prototype verification stage. According to the framework structure of the chip, discrete components are used to design the circuit board. The digital system generally uses the FPGA development platform for prototype development and test verification (common FPGAs are XILINX and ALTERA).
3. The design and verification of analog chips are mainly based on the parameter model provided by the process factory. The performance indicators that can be achieved can only be verified through real chip casting; while the digital system design can generally be fully verified through computer simulation and FPGA system, and then can be directly put into production. Therefore, the development of mixed digital and analog chip products generally requires the analog module to be put into production for verification first, and then the overall production can be carried out after the performance indicator test is passed.
4. After the system development and prototype verification are passed, the chip layout design implementation stage will be entered, which is the digital backend and the splicing with the analog layout. During the layout design process, design verification must be performed, including DRC, LVS, ANT, post-simulation, etc. After the chip layout passes various simulation verifications, a GDS file can be generated and sent to the foundry (or plate-making factory), which is often called tapeout.
5. After the foundry data processing, after obtaining the GDS data, it is necessary to perform DRC inspection again, and then data processing, layer calculation, filling test graphics and other operations, and then send it to the plate-making factory to start plate making. 6. After the plate making is completed, the photolithography plate can be handed over to the foundry for wafer processing.
7. After the wafer processing is completed, it is sent to the mid-test factory for mid-test, also called wafer test (Chip Test, abbreviated as CP). After the mid-test is completed, the failed die on the wafer is marked and handed over to the packaging factory.
8. After the packaging factory performs operations such as wafer thinning, film pasting, dicing, bonding, wire bonding, injection molding, gold cutting, drying, tinning, etc., the packaging is completed. At present, the packaging technology is relatively mature, and the common packaging yield is above 99.5%, or even above 99.9%.
9. Some functions and performances of the chip cannot be tested during the intermediate test, and final test (FT) is required.
10. The chip that has completed the final test can be included in the product library and transferred to the market for sale.
11. The chip research and development process is a process of multiple cycles and iterations. If problems are found during the test and verification process, it is necessary to return to modify the design and then test and verify again; in the back-end layout implementation process, if the timing, power consumption, area, post-simulation, etc. fail, it may also be necessary to return to the original design for modification; after the chip is put out, the test performance indicators and reliability do not meet the design requirements, and it is necessary to analyze and locate the problem, modify the design, and re-test and verify, etc.
12. There are many links in chip research and development, large investment, and long cycle. Any detail that is not considered or wrong may lead to the failure of the chip launch; technology research and development is full of uncertainties, which may lead to time delays and chip launch failures. Therefore, the development of a mature product may require multiple chip launch verifications, resulting in a long cycle.
13. Nowadays, the scale of chip design is relatively large and the system is complex. In order to reduce the risk of chip launch, system design and test verification are very important. On the one hand, it depends on powerful EDA tools, and on the other hand, it depends on experience and personnel time investment.
14. After the chip is transferred to mass production, if the yield is unstable or lower than expected, it is necessary to analyze the reasons with the foundry and adjust the process parameters. After multiple experiments, the most stable process window is found to improve the reliability and yield of the chip and reduce costs.
Schematic diagram of the entire IC R&D and production process

Schematic diagram of the entire IC R&D and production process

Common chip casting methods are engineering batch (FULLMASK) and multi-project wafer (MPW).
With the improvement of manufacturing process level, the cost of manufacturing chips on the production line continues to rise. The production cost of an engineering batch of 0.6 micron process is 200,000-300,000 yuan, while the production cost of an engineering batch of 0.18 micron process is 600,000-1.2 million yuan. If a high-end process is used, the cost of the test piece will increase exponentially. If there is a problem in the design, all the manufactured chips will be scrapped. MPW is to put multiple integrated circuit designs with the same process on the same wafer for tape-out. After tape-out, each design variety can get dozens of chip samples, which is enough for experiments and tests in the design and development stage. The experimental cost is shared by all projects participating in MPW according to the chip area, and the cost is only 10%-20% of the engineering batch, which greatly reduces the cost and risk of new product development. MPW is generally organized by the process factory and has regular shifts every year. Although MPW has lowered the cost threshold for integrated circuit R&D, it is also accompanied by some constraints such as low flexibility in wafer casting, long production cycle, and unit area restrictions.
The specific wafer casting method needs to be selected based on the design success rate, capital budget, and time cycle. Comparison table of the two voting methods:

combat

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紫色系0120

Thanks for sharing!