Internal structure problem of SG2525A chip

shaorc

As shown in Figure 1, this is the internal diagram of the SG2525 driver chip

[1] As mentioned in Figure 2 (yellow line), the output of the oscillator inside Figure 1 is divided into two paths. One path is in the form of a clock pulse and is sent to the subsequent logic gate circuit, and the other path is in the form of a sawtooth wave and is sent to the same-direction end of the internal comparator.

As can be seen from Figure 1, the signal sent to the internal comparator comes from the input pin Ct. How can it be said to come from the output of the oscillator?

[2] As shown in Figure 2 (the yellow line at the bottom), one of the input signals of the NOR gate comes from the sawtooth wave output of the oscillator. But didn’t we say before that the sawtooth wave is sent to the same-direction terminal of the internal comparator?

Figure 1

Figure 2

maychang

[1] As mentioned in Figure 2 (yellow line), the output of the oscillator inside Figure 1 is divided into two paths. One path is in the form of a clock pulse and is sent to the subsequent logic gate circuit, and the other path is in the form of a sawtooth wave and is sent to the same-direction end of the internal comparator.

As can be seen from Figure 1, the signal sent to the internal comparator comes from the input pin Ct. How can it be said to come from the output of the oscillator?

Not reading carefully.

The article states very clearly: the oscillator output is divided into two paths, one is in the form of a clock pulse and sent to the subsequent logic gate circuit (indicated by blue in the figure below), and the other is in the form of a sawtooth wave and sent to the same-direction end of the internal comparator (indicated by red in the figure below).

maychang

As can be seen from the second floor picture: the red signal and the blue signal are connected to the outside of the chip, the red signal is connected to pin 5, and the blue signal is connected to pin 4. After the chip is connected to the external components, the waveforms of pins 4 and 5 can be seen with an oscilloscope after powering on. The waveform of pin 4 is a narrow pulse, and the waveform of pin 5 is similar to a sawtooth wave.

maychang

[2] As shown in Figure 2 (the yellow line at the bottom), one of the input signals of the NOR gate comes from the sawtooth wave output of the oscillator. But didn’t we say before that the sawtooth wave is sent to the same-direction terminal of the internal comparator?

The "one of the input signals of the NOR gate comes from the sawtooth wave output of the oscillator" mentioned here refers to the signal that the sawtooth wave passes through the output of the comparator (rectangular wave) and is then latched by the latch, as shown in green in the figure below.

maychang

The parts responsible for generating rectangular pulses (PWM waves) are the parts marked "PWM" and "Latch" in the figure above, the blue line is responsible for generating the "dead zone", and the part marked "F/F" (Flip/Flop) in the figure is responsible for the two alternating outputs.

shaorc

maychang posted on 2020-9-18 11:39 The part responsible for generating the rectangular pulse (PWM wave) is the part marked "PWM" and "Latch" in the figure above, which is responsible for...

In the actual circuit of SG2525, a capacitor is connected to the CT pin and a resistor is connected to the RT pin to determine the oscillation frequency.

[3] However, the information says that a resistor is connected in series between the CT pin and the Discharge pin to set the dead time. In the fifth post, it is mentioned that the blue line part generates the dead time. What is the principle behind this?

[4] Is the working principle of pin 7 (discharge) that when the internal transistor connected to it (the transistor surrounded by the red line in the second floor figure) is turned on, the charge of the oscillation capacitor connected to the CT pin is released, thereby stopping SG2525 from working?

maychang

shaorc posted on 2020-9-19 07:59 In the actual circuit of SG2525, a capacitor is connected to the ground at the CT pin, and a resistor is connected to the ground at the RT pin to determine the oscillation frequency. [3] However, the data...

"In the actual circuit of SG2525, a capacitor is connected to the ground at the CT pin, and a resistor is connected to the ground at the RT pin to determine the oscillation frequency."

Strictly speaking, the oscillation frequency is determined by three components: the capacitance from the CT pin to ground, the resistance from the RT pin to ground, and the resistance between pins 7 and 5.

maychang

shaorc posted on 2020-9-19 07:59 In the actual circuit of SG2525, a capacitor is connected to the ground at the CT pin, and a resistor is connected to the ground at the RT pin to determine the oscillation frequency. [3] However, the data...

The resistance (RT) between pin 6 and ground determines the charging current of the capacitor (CT) through the internal circuit of the oscillator. As can be seen from the left side of the figure below, the larger the resistance, the longer the capacitor charging time. Pin 7 is used to discharge the capacitor (this is exactly your [4] question). As can be seen from the right side of the figure below, the larger the resistance between pin 7 and pin 5, the longer the capacitor discharge time (that is, the longer the dead time). The resistance between pin 7 and pin 5 is allowed to be zero (short circuit), at which time the discharge is the fastest and the dead time is the shortest. However, the circuit between pin 7 and pin 5 is not allowed to be open, otherwise the capacitor cannot be discharged and oscillation cannot occur.

The connections of these three pins and the three components are shown in the lower right corner of the above picture.

Therefore, the oscillation frequency is determined by RT, CT and RD.

maychang

shaorc posted on 2020-9-19 07:59 In the actual circuit of SG2525, a capacitor is connected to the ground at the CT pin, and a resistor is connected to the ground at the RT pin to determine the oscillation frequency. [3] However, the data...

[4] Is the working principle of pin 7 (discharge) that when the internal transistor connected to it (the transistor surrounded by the red line in the second floor figure) is turned on, the charge of the oscillation capacitor connected to the CT pin is released, thereby stopping SG2525 from working?

It cannot be said that "SG2525 stops working". The capacitor discharge is just the voltage across the capacitor returning to its original state and starting the next oscillation cycle.

maychang

shaorc posted on 2020-9-19 07:59 In the actual circuit of SG2525, a capacitor is connected to the ground at the CT pin, and a resistor is connected to the ground at the RT pin to determine the oscillation frequency. [3] However, the data...

The "dead zone" is not the time when both switches are off, but the time when the error amplifier output is positively saturated (PWM duty cycle reaches the maximum at this time), and both outputs (pin 11 and pin 14) are low for a period of time. In other words, the dead zone is the time when the duty cycle is the maximum and no output is high. In fact, in SG3525A, it is slightly longer than the capacitor discharge time, so the capacitor discharge time can be considered as the dead zone time. This can be seen with an oscilloscope.

If the error amplifier output is not forward saturated, the dead time remains the same, but the PWM comparator in the third floor diagram flips and is locked by the latch before the capacitor is discharged by pin 7, and both outputs (pins 11 and 14) are low.

guyanqiu

https://html.alldatasheet.com/html-pdf/70476/LINER/SG1524/905/7/SG1524.html

There is an older datasheet of LT1524, which has the internal schematic diagram of the oscillator part, where RT and CT are. RT is used to set the current of the constant current source that charges CT, and then the constant current source charges CT. At this time, the charging current is constant, so the CT is a triangular wave. When the CT voltage is charged to a certain level, the voltage on CT is higher than the internal comparator input, and then the discharge circuit connected to CT will work, and CT will discharge quickly, so the waveform should be an oblique sawtooth wave.

The oscillator part of SG3525 should be the same. I personally think it is better to have a complete internal structure. It seems that except for this relatively old datasheet on the Internet, which is a complete internal schematic diagram, the others are in the form of block diagrams, which makes it difficult to understand the working principle of the oscillator part.

shaorc

guyanqiu posted on 2020-9-22 07:22 https://html.alldatasheet.com/html-pdf/70476/LINER/SG1524/905/7/SG1524.html There is an older LT1524 ...

Thanks for sharing

shaorc

maychang posted on 2020-9-19 15:14 shaorc posted on 2020-9-19 07:59 In the actual circuit of SG2525, a capacitor is connected to the CT pin and a resistor is connected to the RT pin to the ground to determine...

Can you explain in detail here, how to discharge CT by connecting a resistor in series between pins 5 and 7 to achieve the dead zone effect? Since the PWM duty cycle is the largest, why do both outputs (pins 11 and 14) still output low level after passing through the comparator? How does the discharge of CT affect the high and low level of the outputs of pins 11 and 14? Seeing what you said below, is it related to the latch in SG3525?

"If the error amplifier output is not forward saturated, the dead time remains the same, but the PWM comparator in Figure 3 flips and is latched before the capacitor is discharged by pin 7, and both outputs (pins 11 and 14) are low."

maychang

shaorc posted on 2021-1-19 09:29 Can you explain in detail here, discharge the CT through a series resistor between pins 5 and 7 to achieve the dead zone effect, since both are PWM duty cycles...

"Is what you said below related to the latch in SG3525?"

This is a long story, so I will explain it later after I draw the curve.

shaorc

maychang posted on 2021-1-19 12:16 "Seeing what you said below, is it related to the latch in SG3525? ” This matter is quite long to talk about. Wait for me...

OK, please let me know when you update your answer to this question, thank you

maychang

shaorc posted on 2021-1-21 08:43 Ok, when you update the answer to this question, please let me know, thank you

The figure above shows six lines of waveforms. Needless to say, the horizontal axis is time and the vertical axis is voltage, but the vertical axis has only relative meaning. Except for the first line, it only represents high and low levels, so the unit is not marked.

maychang

shaorc posted on 2021-1-21 08:43 OK, please let me know when you update the answer to this question, thank you

The first line of the 16th floor figure is the waveform at the mark (1) in the figure above, that is, the waveform at both ends of the external timing capacitor. The voltage rise and fall at both ends of the capacitor are exponential curves. For simplicity, this figure is drawn as a straight line. It can be seen from the 16th floor figure that this is an approximate sawtooth wave. The rise is due to the external resistor charging the capacitor, and the fall is due to the internal transistor of the chip discharging the capacitor. The dotted line in the first row of waveforms is the output voltage of the error amplifier EA. Because the output of the error amplifier EA cannot change very quickly, the dotted line is approximately horizontal. In fact, the output voltage of the error amplifier EA changes slowly, that is, the dotted line will slowly rise or fall.

maychang

shaorc posted on 2021-1-21 08:43 Ok, when you update the answer to this question, please let me know, thank you

The 16th floor, row (2) corresponds to the 17th floor, point (2) waveform, which is the waveform at the output of the oscillator circuit. Note that the waveform at this point is at a high level when the sawtooth wave is falling.

maychang

shaorc posted on 2021-1-21 08:43 Ok, when you update the answer to this question, please let me know, thank you

The waveform in row (3) on the 16th floor corresponds to the waveform at point (3) on the 17th floor, i.e. the output waveform of the PWM part.

PWM is actually a comparator. However, the polarity of the three input terminals is not given in the figure on the 17th floor. From the figure below, we can see that among the three input terminals, the top one is the non-inverting input terminal, and the middle one and the bottom one are the inverting input terminals.

Let's ignore the lower input terminal for now and only look at the upper and middle two input terminals. The upper input terminal is connected to the timing capacitor, and the lower input terminal is connected to the output terminal of the error amplifier EA. So we can conclude that: when the voltage across the timing capacitor is higher than the voltage at the output terminal of the error amplifier, the PWM comparator output is high level. This is exactly the waveform of row (3) on the 16th floor.

maychang

shaorc posted on 2021-1-21 08:43 Ok, when you update the answer to this question, please let me know, thank you

There are two "NOR" gates A and B in Figure 17, each with three input terminals. The upper input terminals of A and B are connected to the complementary output terminals of Filp-Flop.

For now, let's ignore the input terminals of A and B and treat A and B as two-input NOR gates. Then, according to the "NOR" characteristic, if either input terminal of A or B is high, the output is low. The so-called "high or low", the output waveform of A or B should be like the waveform of row (4) on the 16th floor. The relationship between the waveform of row (4) on the 17th floor and the waveforms of rows (2) and (3) must be understood. Row (4) is the result of the "NOR" logic operation of rows (2) and (3).