Discussion on Digital Phase-locking Technology of DSP

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Discussion on Digital Phase-locking Technology of DSP [Copy link]

The requirements for power supply quality and reliability of power supply systems are getting higher and higher, and the application of uninterruptible power supplies (UPS) is becoming more and more widespread. Since online UPS needs to switch between bypass power supply and inverter power supply, in order to achieve continuous switching, it is necessary to synchronize the inverter output voltage with the bypass voltage through a synchronous phase lock. For the same reason, phase lock synchronization is also necessary when multiple UPS are connected in parallel and multiple UPS form a redundant system. The inverter output phase of the UPS can be consistent with the mains, but the amplitude of the output waveform must be consistent, which violates the function of the UPS. Therefore, the goal of UPS phase lock is usually to keep the amplitude approximately equal while ensuring the phase consistency.

　　Phase locking can be divided into analog phase locking and digital phase locking. Compared with traditional analog phase locking, digital phase locking can not only simplify the hardware circuit and reduce the cost, but also solve the problems of aging and temperature drift of components in analog circuits, and improve the accuracy of phase locking. This article discusses digital phase locking technology based on DSP.

　　1 Digital phase locking algorithm

　　There are many ways to achieve phase tracking. One method is to use the mains voltage as the synchronization signal. This method is relatively simple to implement and can lock the phase in a very short time. However, since the mains voltage is not a standard sine wave, the frequency will deviate. The commonly used phase-locking method is to convert the phase difference into a voltage, and then use this voltage to control a voltage-controlled oscillator to achieve it. The basic structure of analog phase lock (APLL) and digital phase lock (DPLL) is similar, including four parts: phase detector (PD), low-pass filter, voltage-controlled/digital-controlled oscillator (VCO/DC0) and divider, as shown in Figure 1. There are many ways to achieve digital phase lock, such as the control of single-cycle digital PLL.

　　For UPS, the basic phase-locked circuit can obtain a signal true φo that is consistent with the input voltage phase frequency, and then use the signal φo to adjust the reference sinusoidal voltage signal of the inverter. As a result, the output voltage can maintain the same frequency as the input voltage, but there is a fixed phase difference. This is due to the influence of many factors such as the inverter sampling link, correction link, output filter and load. The structure of the PLL used in this article is shown in the dotted box in Figure 2. The input phase signal φi is the mains phase, and the feedback phase signal φc is the inverter output capacitor voltage phase.

　　The phase detector outputs a result that is proportional to the phase difference, and the proportionality coefficient is Kd, then:

　　The impulse transfer function of the filter is set to F(z). Butterworth, Chebyshev and other filters can be used. Proportional integral links or other links are often used to replace low-pass filters. This article uses a proportional integral link, namely:

　　Here, the digital controlled oscillator is a name that is usually used. In fact, there is no oscillating component, but a proportional amplification link. After proportional amplification, φf is added to the input signal period (Tin) to obtain the phase-locked output signal period To=Tin+Koφf, and the output phase is φ=Koφf. Assuming that the pulse transfer function of the link outside the phase-locked loop is G(z), the pulse transfer function of the entire system is:

　　In this UPS, it is difficult to determine the expression of C(z) by actual circuit and program. During design, we can approximately determine G(z) as a hysteresis link with very small delay based on the simulation results of the inverter, or simply ignore its influence.

　　2 Digital phase locking using DSP

　　DSP is a unique microprocessor that processes large amounts of information using digital signals. Its working principle is to receive analog signals and convert them into digital signals of 0 or 1. It then modifies, deletes, and strengthens the digital signals, and interprets the digital data back into analog data or actual environment formats in other system chips. It is not only programmable, but also has a real-time running speed of tens of millions of complex instruction programs per second, far exceeding general-purpose microprocessors. It is an increasingly important computer chip in the digital electronic world. Its powerful data processing capabilities and high operating speed are the two most commendable features.

　　In the phase-locked link, only the phase detection of the phase detector is completed by the hardware circuit, and the others are implemented by software in the DSP. The phase detection circuit is shown in Figure 3. The comparator U2B and some peripheral components constitute a zero-crossing comparator with hysteresis. The size of the hysteresis mainly depends on anti-interference considerations. The interference to the control circuit when the inverter is switched is very serious. It is better to obtain a larger hysteresis, but too large a hysteresis will cause the phase detection error to increase. Therefore, the selection of the hysteresis size needs to be considered. In the actual circuit. Due to the existence of interference near zero crossing, the output is a signal with a high frequency flip between "0" and "1", so de-jittering processing is required in the phase detection of the program.

　　The frequency is determined by the count value between two zero-crossing signals in the program, that is, the cycle value represented by the juice value. The count is performed once in each interrupt cycle, and each count unit represents 50μs, 20ms is 400 calculation units, and the phase difference is also obtained by counting. In order to prevent the inverter output frequency from being too large or too small, the calculation result of the output cycle must be limited in amplitude. At the same time, the amplitude of the adjustment should also be limited to avoid drastic changes in the output frequency.

　　The end of the PLL subroutine also includes the reference waveform generation part in Figure 2, and the entire program flow is shown in Figure 4.

　　3 Experimental Results

　　The above method is used to realize the phase lock between the inverter output and the mains input in TMS320F240. The phase lock result is captured by TDS210 oscilloscope, as shown in Figure 5. In Figure 5, the higher amplitude 2 is the inverter output voltage waveform, measured by a 100:1 probe, and the lower amplitude 1 is the input mains waveform, which is measured by a 500:1 differential probe (because the oscilloscope does not have a 500:1 probe setting. This channel is regarded as a 1:1 probe during measurement, so the actual oscilloscope measurement corresponding to waveform 1 is 250V/div, not 500mV/div as shown in the figure).

　　The phase-locking process can be clearly seen from Figure 5. Initially, the inverter output phase is ahead of the AC power, so a relatively large output cycle is used to gradually lock the input voltage phase. After locking, the output is output with the same cycle as the input voltage, achieving the same frequency and phase.

　　4 Conclusion

　　This paper analyzes and discusses the digital phase-locking technology in the inverter, and implements the digital phase-locking of the inverter with DSP. The experiment shows that the inverter output can well achieve synchronous phase-locking, so that the UPS can safely switch between inverter power supply and bypass power supply, thereby improving the reliability of the UPS power supply system.