Playing with Zynq Serial 22——[ex03] PLL configuration example based on Zynq PL

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Playing with Zynq Serial 22——[ex03] PLL configuration example based on Zynq PL [Copy link]

1 Overview

This example uses clocks of different frequencies generated by PLL to drive three LED indicators to flash at the same frequency. The focus of this example is not the LED , but the application of the IP core. Of course, only the PLL IP core is used as an example.

2 Modular Design

Reference document "Playing with Zynq- Basics : Modular Design Based on FPGA.pdf ".

3 PLL IP core add configuration

3.1 Overview of Vivado Standard IP Core

The IP cores we often talk about , or intellectual property , are those verified, reusable design function modules with certain functions. IP cores are generally divided into soft IP cores , firm IP cores , and hard IP cores . Soft IP uses a high-level language to describe the behavior of the function block, but does not involve what circuits and circuit components are used to implement these behaviors. In addition to completing all the designs of soft IP , firm IP also completes design links such as gate circuit level synthesis and timing simulation, and is generally submitted to users in the form of gate circuit level netlists. Hard IP completes the integrated function blocks, has a fixed topology layout and specific process, and has been verified by the process, with guaranteed performance. The deeper the design, the less things need to be done in the subsequent processes, but the less flexibility there is .

In Xilinx 's FPGA devices, IP core design is a very important and indispensable part. It should be said that the aforementioned soft IP , fixed IP and hard IP can all be found on the Zynq on our Zstar board . As for Vivado , for the IP provided by Xilinx or its third-party partners, which has been integrated into the Vivado tool interface for designers to call , we can call it a standard IP core; and for the IP core that is not integrated in Vivado and is developed and designed by a third party or the user himself , we call it a user-defined IP core.

For the IP cores integrated in Vivado , you can click the Vivado menu Window --> IP Catalog to view them.

In the Vivado main window, IP Catalog --> Cores lists the classified IP cores that Vivado has integrated . Click the + sign in front of each category to view which IP cores are available in that specific category .

For general IP cores, first find the required IP core, then double-click the IP core to pop up the configuration page. After the configuration is completed, various IP core related design files are output. In the user design, just instantiate the IP core module.

Let's take the configuration of the PLL IP core of the zstar_ex04 instance as an example to see how to add and configure the standard IP core integrated in Vivado .

3.2 PLL IP Core Configuration Example

As shown in the figure, click "Project Manager -> IP Catalog" under the Flow Navigator panel .

Figure IP Catalog menu

As shown in the figure, the pop-up IP Catalog panel lists the classification list of all Vivado's built-in IP cores.

Figure 1. IP Catalog panel

As shown in the figure, after expanding the "FPGA Features and Design -> Clocking" category, you can see the IP core called Clocking Wizard . Through this IP core, we can configure a PLL to perform various frequency division or frequency multiplication processing on the FPGA external input clock. Click Clocking Wizard and the corresponding configuration page will pop up.

Figure Clocking Wizard IP core

The first configuration page that pops up is shown in the figure. Here, you can select "PLL" for Primitive , and then set our input clock frequency ( Input Frequency ) to 25MHz in the Primary row of the clock frequency ( Input Clock Information ) .

Figure Clocking Options configuration page

Then in the Output Clocks configuration page, as shown in the figure, check the three clocks clk_out1/2/3 and set their output frequencies to 25MHz , 50MHz , and 100MHz respectively . At the same time, check the control signals reset and locked , and they are active high .

Figure Output Clocks configuration page

No configuration changes are required on the next few pages. Simply click OK to complete the PLL configuration.

After the configuration takes effect, we can switch to the IP Sources subpage under the Sources panel. As shown in the figure, an IP core named clk_wiz_0 appears, which is the IP core we just configured and added . You can click to expand it . The "clk_wiz_0.veo" file under "Instantiation Template" is the instantiation template, which can be double-clicked to open.

Figure View instantiation template

As shown in the figure, we can copy the instantiation template of this PLL and modify the external interface accordingly in our project.

Figure PLL instantiation template

The interface definition of the PLL module here is shown in the table.

Signal name	direction	Functional Description
clk_in1	enter	The input clock signal of the PLL module is the base frequency of all output clocks.
clk_out1	Output	Output clock 1 of the PLL module .
clk_out2	Output	Output clock 2 of the PLL module .
clk_out3	Output	Output clock 3 of the PLL module .
reset	enter	The input reset signal of the PLL module is valid at high level.
locked	Output	The PLL lock indication signal is valid at high level, that is, when the signal is at high level, it indicates that the PLL output clock has been output normally.

Note: The direction is relative to the PLL module.

4 PLL IP core migration

Reference document "Playing with Zynq- Tools : IP core porting in Vivado.pdf ".

5. Board-level debugging

Refer to the document "Playing with Zynq- Environment: XilinxPlatformCableUSB Downloader User Guide" to burn the zstar.bit file in the ...\project\zstar_ex03\zstar.runs\impl_1 path into Zynq .

The effect you see is that the three LED indicators D1 , D2 and D3 flash synchronously.

This content is originally created by EEWORLD forum user ove . If you want to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source