1 Overview
The buzzer is the simplest sound-generating component, and it is widely used, mostly as an alarm or sound reminder device. For example, when a desktop computer is just turned on, the motherboard usually emits a short, sharp " beep ..." beep, prompting the user that the motherboard self-test has passed and the subsequent startup can proceed normally; if it is a long and a short beep or a long and two short beeps, it means that the computer memory or graphics card may have a fault; of course, there may be other different beeps to indicate other faults. In short, don't underestimate this buzzer that costs only a few cents, it is quite useful at critical moments. It is no exaggeration to say that the buzzer is also a means of human-computer interaction.
PWM ( Pulse Width Modulation ) is pulse width modulation. As shown in the figure, the output of PWM is only high level 1 and low level 0. PWM continuously repeats the output cycle of T , where the high level 1 time is t , t/T is its duty cycle, and 1/T is its frequency.
As shown in the figure, this is the circuit schematic of the buzzer on the Zstar board. The BEEP network is connected to the IO of the FPGA . When BEEP = 1 , the BE of the transistor Q1 is turned on, and the CE is also turned on, and the buzzer U2 has a current loop, so the buzzer will sound. Similarly, when BEEP = 0 , Q1 is cut off, the buzzer has no current loop, and the buzzer will not sound.
As shown in the figure, based on the principle that the buzzer sounds when the FPGA IO output is 1 and does not sound when it is 0 , we give the IO port a PWM signal with a duty cycle of 10% to make the buzzer sound intermittently. If its frequency is high, the sound will be relatively sharp and rapid; if its sound frequency is low, the sound will be low and smooth.
In the example code we give, we expect to generate a PWM signal with an output frequency of 1Hz ( 1s ) and a duty cycle of 10 % to drive the buzzer to sound. Therefore, we use the system clock 25MHz for counting, and the counter is cleared and recalculated every 25,000,000 counts. Because this counter is binary , to be able to express every count value from 0 to 24,999,999 , the binary counter must be at least 25 bits (the counter is taken as 28 bits in the code). In addition, in order to get the output PWM duty cycle of 10% , we only need to judge that when the count value is less than 1/10 of the maximum count value, that is, 2,500,000 , the output is a high level 1 , otherwise the output is a low level 0 .
The most basic steps to create an application project that can eventually run on the Zynq PL can be summarized as follows. We will practice them one by one below. The process is just a process of practice makes perfect. As long as you go through it carefully, keep practicing in a large number of subsequent examples, and practice repeatedly, you will easily master it.
2. Create a new Vivado project
Refer to the document "Playing with Zynq- Tools: Creating a New Vivado Project.pdf " .
3. Create project source code
As shown in the figure, select Project Manager à Sources à Design Sources , right-click, and select Add Sources… in the pop-up menu .
Figure 1. New Verilog source code menu
Then, as shown in the figure, use the default option Add or create design sources and click "Next" .
Figure Select File Type
Click the Create File button as shown .
Figure 1. New design file
As shown in the figure, set the created file type ( File type ) to Verilog ; the file name ( File name ) to zstar ; and the file location ( File location ) to the default <Local to Project> .
Figure 1. Setting the new file name and path
Finally, click the Finish button to complete the creation of the Verilog source file.
Then the module port setting page as shown in the figure will pop up. You can just click OK without making any settings.
Graph Definition Module
Then a confirmation dialog box will pop up as shown in the figure, click Yes .
Diagram Definition Module Confirmation Dialog Box
As shown in the figure, double-click the zstar.v file just created under Design Sources , and the source code will pop up, which contains the basic Verilog module definition. The content is empty and needs to be filled in.
Figure 1. Created Verilog source file
As shown in the figure, fill in the Verilog code to implement a complete design source code module.
Figure Verilog source code
4 Create constraints file
As shown in the figure, select Project Manager -> Constraints -> constrs_1 , right-click, and select Add Sources… in the pop-up menu .
Figure 1. New Constraint File Menu
Then, use the default option Add or create constraints as shown .
Figure Select File Type
Click the Create File button as shown .
Figure 1. New design file
As shown in the figure, set the created file type ( File type ) to XDC ; the file name ( File name ) to zstar ; and the file location ( File location ) to the default <Local to Project> .
Figure 1. Setting the new file name and path
Finally, click the Finish button to complete the constraint file creation.
As shown in the figure, double-click the zstar.xdc file just created under Constraints , which is completely blank.
Figure 1. Created constraint source file
As shown in the figure, write all the pin constraints of this instance into this constraint file. From the simple syntax, we can see that the top-level interface signal in zstar is constrained to correspond to the pin number ( PACKAGE_PIN ) and level standard ( IOSTANDARD ) of the Zynq chip.
Figure Pin Constraint Script
As shown in the figure, the newly generated zstar.srcs\source_1 and zstar.srcs\constrs_1 folders in the project path correspond to the Design Source and Constraints in the Project Manager respectively.
The corresponding folder under the project path
5 Functional simulation
Reference document "Playing with Zynq : Functional Simulation of PL in Vivado.pdf " .
6. Compilation
As shown in the figure, Vivado compilation is mainly divided into three steps, namely Run Synthesis , Run Implementation and Generate Bitstream . Generally speaking, we can directly click Generate Bitstream to generate the bit file and then perform board-level debugging.
Figure Compile Menu
During the compilation process, as shown in the figure, there is an indication of the current compilation status in the upper right corner of the Vivado tool.
Figure compilation status information
As shown in the figure, after the compilation is completed, a prompt option window will pop up, which has multiple options for the next step. You can directly click Open Hardware Manager to enter the board-level download and debugging interface.
The selection window after the bitstream is generated
As shown in the figure, the zstar.bit file is generated under the project path “…/project/zstar_ex01/zstar.uns/impl_1” , which is the bit stream used to burn into the FPGA for online operation.
The bit file generated by the graph
7. Board-level debugging
Refer to the document "Playing with Zynq- Environment: XilinxPlatformCableUSB Downloader User Guide.pdf " for board-level debugging.
This content is originally created by EEWORLD forum user ove . If you want to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source
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