DSP Learning (1) Introduction to Digital Signal Processors (DSPs)

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Chapter 1 Introduction to Digital Signal Processors (DSPs)

Real-time signal processing systems must be able to process large amounts of data to ensure the real-time performance of the system; secondly, they also have strict requirements on the size, power consumption, stability, etc. of the system. Real-time signal processing algorithms often use different levels and types of processing such as image summation and difference operations, two-dimensional gradient operations, image segmentation and regional feature extraction. Some of the operations themselves have a relatively simple structure, but the data volume is large and the calculation speed is high; some processing does not have special requirements for speed, but the calculation method and control structure are relatively complex and difficult to implement with pure hardware. Therefore, the real-time signal processing system is a comprehensive information processing system with high requirements for calculation speed and many types of operations.
In the real-time signal processing system, the low-level signal preprocessing algorithm processes a large amount of data and has high requirements for processing speed, but the calculation structure is relatively simple, which is suitable for hardware implementation with FPGA, so that both speed and flexibility can be taken into account. The characteristic of high-level processing algorithms is that the amount of data processed is less than that of low-level algorithms, but the control structure of the algorithm is complex, which is suitable for implementation with DSP chips with high calculation speed, flexible addressing mode and powerful communication mechanism. As a result, various DSP digital signal processing chips came into being.

There are significant differences between DSP and general-purpose processors (GPPS) such as Intel Pentium or Motorola PowerPC. These differences arise from the fact that the structure and instructions of PSS are designed and developed specifically for signal processing and have the following characteristics.

Hardware Multiply-Accumulate Operations (MACs)
The first major technology advancement that differentiated DSPs from early GPPs was the addition of dedicated hardware and explicit MAC instructions capable of single-cycle multiplication operations.

Harvard Architecture
Traditional GPPs use a von Neumann memory architecture, in which there is a memory space connected to the processor core by two buses (one address bus and one data bus). This architecture does not meet the requirement that the MAC must access the memory four times in one instruction cycle. DSPs generally use the Harvard architecture, in which there are two memory spaces: program memory space and data memory space. The processor core is connected to these memory spaces by two sets of buses, allowing two simultaneous accesses to the memory. This arrangement doubles the bandwidth of the processor. In the Harvard architecture, greater memory bandwidth is sometimes achieved by adding a second data memory space and bus. Modern high-performance GPPs usually have two on-chip ultra-high-speed cache memories, one for data and one for instructions. From a theoretical perspective, this dual on-chip cache and bus connection is equivalent to the Harvard architecture, but GPPs use control logic to determine which data and instruction words reside in the on-chip cache. This process is usually invisible to the programmer, while in DSPs, the programmer can explicitly control which data and instructions are stored in the on-chip memory cells or caches.

Zero-cost loop control
A common feature of DSP algorithms is that most of the processing time is spent executing a small number of instructions contained in relatively small loops. Therefore, most DSP processors have dedicated hardware for zero-cost loop control. A zero-cost loop is a loop in which the processor executes a set of instructions without spending time testing the value of the loop counter. The hardware performs loop jumps and loop counter decay. Some DSPs also implement high-speed single-instruction loops by using an ultra-high-speed cache of one instruction.

· Special addressing modes
DSPs often contain special address generators that can generate special addressing required by signal processing algorithms, such as circular addressing and bit-flip addressing. Circular addressing corresponds to the pipeline FIR filter algorithm, and bit-flip addressing corresponds to the FFT algorithm.

Most DSP applications have hard real-time requirements, where
all processing work must be completed within a specified time in every case. This real-time constraint requires the programmer to determine how much time each sample will take or at least how much time it will take in the worst case. The DSP's execution process is transparent to the programmer, so it is easy to predict the execution time of each processing task. However, for high-performance GPPs, the prediction of execution time becomes complicated and difficult due to the use of large amounts of ultra-high-speed data and program caches and dynamic allocation of programs.

· Rich peripherals
DSPs have DMA, serial port, PLL, timer and other peripherals.