【Qinheng Trial】3. System clock and TIMER0

lising

【Qinheng Trial】3. System clock and TIMER0 [Copy link]

This experiment uses the internal timer resources of CH549 to generate timing and control the onboard LED flip to produce a flashing effect. The main purpose of the experiment is to learn more about the clock system and timer resources of CH549.

1. Experimental resources
1. CH549EVT learning development board;
2. Keil v5.28.0.0;
3. CH549 development data summary.rar;
4. WCHISPTool v2.70;

5. Other relevant documents of CH549EVT;

6. Logic analyzer;

For more information, please visit Jiangsu Qinheng Co., Ltd. http://wch.cn/

2. Experimental Preparation

1. Understand the clock system of CH549. The following is the clock system and structure diagram of CH549:

From the above figure, we can intuitively understand that CH549 has two options for the clock, namely the internal clock 24MHz and the external crystal oscillator. The choice is set by the "bOSC_EN_INT" of the clock control register "CLOCK_CFG". The reset value of "CLOCK_CFG" is "0X83", that is, bOSC_EN_INT＝1 uses the internal clock 24MHz. The selected clock is used as the original clock and multiplied by PLL. Fpll is divided into two paths: one is divided by the USB clock divider for USB devices; the other is divided by the [2:0] "MASK_SYS_CK_SEL" system clock divider of "CLOCK_CFG". The divided system clock "Fsys" is used for other resources of CH549. Of course, for some modules, further division processing can be performed according to different usage requirements. The "MASK_SYS_CK_SEL" system clock divider can divide "Fpll" into eight types, providing great flexibility for application.

Through study and understanding, we can see that the clock system of CH549 is powerful and flexible in application, which facilitates the design and application of products.

2. Timer resources. CH549 has three sets of standard 51 timers, T0/T1/T2. This experiment uses the timer mode 1 of TIMER0 and enables interrupts. The following is the system diagram of TIMER0:

As can be seen from the figure, mode 1 has multiple options for timing clock, which can be configured through the relevant bits "bTMR_CLK" and "bT0_CLK" of the register "T2MOD". The reset value of "T2MOD" is "0X00", which makes the application of timing/counting more flexible.

3. GPIO port. The GPIO function of CH549 has also been greatly improved compared with the traditional 51, making GPIO more flexible and convenient for different applications. It is mainly reflected in the addition of the output mode register "Pn_MOD_OC" of the GPIO port. By configuring it, the GPIO port can be configured as "push-pull output" or "open-drain output"; the input and output direction selection of the GPIO port and the pull-up resistor enable control in the "open-drain output" mode have been added. By configuring the port direction control and the pull-up enable register "Pn_DIR_PU", the GPIO port can be set to "input" or "output" in the "push-pull output" mode; or the GPIO port can be set to "enable pull-up resistor" or "disable pull-up resistor" in the "open-drain output" mode. All these make the GPIO function more powerful and more flexible.

3. This experiment.

1. Resource allocation

Use timer T0 to generate a 50ms interrupt, and in the interrupt function, invert the LED connected to P22 to make it flash. For the convenience of the experiment, set CLOCK_CFG = 0X83 (system reset value), that is, use the internal clock Fosc = 24MHz, Fsys = 12MHz; T2MOD = 0X00 (system reset value), that is, "bT0_CLK = 0", and the internal clock frequency of T0 selects the standard clock Fsys/12.

2. Program implementation

The program is relatively simple, and the registers are configured directly according to the manual:

#include "CH549.H"

sbit D2 = P2^2;
sbit D3 = P2^3;
sbit D4 = P2^4;
sbit D5 = P2^5;

void CLK_Config(void)
{
  CLOCK_CFG = 0x83;
}

void GPIO_Config(void)
{
	P2_MOD_OC &= ~(D2|D3|D4|D5);//设置P2.2、P2.3、P2.4、P2.5为推挽输出
	P2_DIR_PU |= (D2|D3|D4|D5); 
}

void TIMER0_Config(void)
{
	//bTMR_CLK=1使用没有分频的系统主频Fsys作为计数时钟；
	//bTMR_CLK=0使用分频的系统主频Fsys作为计数时钟；
	//bT0_CLK=0 选标准时钟Fsys/12；
	//bT0_CLK=1 选快速时钟Fsys/4(bTMR_CLK=0)或 Fsys(bTMR_CLK=1)；
	
	T2MOD = 0X00;		
	TMOD = 0X01;	//配置TIMER0为定时器工作方式1（16位）
	TH0 = (65536-50000)/256;
	TL0 = (65536-50000)%256;

	TR0 = 1;			//启动TIMER0
	ET0 = 1;			//TIMER0中断允许
	EA = 1;				//全局中断使能
}

void main(void)
{
	CLK_Config();
	GPIO_Config();
	TIMER0_Config();
	while(1)
	{	
	}
}

void TIMER0_ISR(void) interrupt 1
{
	TH0 = (65536-50000)/256;
	TL0 = (65536-50000)%256;
	D2 = ~D2;
}

IV. Experimental Results

5. Experimental Summary

Through this experiment, I have a deeper understanding of CH549's system clock, timer T0, GPIO configuration, timer interrupt, etc., which is a warm-up for the experimental study of other powerful resources of CH549.


This content is originally created by lising, a netizen of EEWORLD forum. If you want to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source

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