Design of Video Image Acquisition Interface for TMS320C54x DSP

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Design of Video Image Acquisition Interface for TMS320C54x DSP [Copy link]

This paper introduces a black and white TV signal acquisition circuit based on DSP. The circuit consists of a communication video A/D converter. The DSP starts the A/D conversion and reads the A/D conversion result. The circuit structure is simple, low cost, easy to implement, and can meet the needs of black and white TV signal acquisition. Keywords: video image acquisition A/D conversion DSP TMS320C54x

Introduction
There are many methods for video image acquisition, which can basically be divided into two categories: automatic image acquisition and processing-based image acquisition. The former uses a dedicated image acquisition chip to automatically complete image acquisition, frame memory address generation and image data refresh; except for setting the acquisition mode, the main processor does not participate in the acquisition process. The characteristics of this method are that the acquisition does not take up CPU time, has good real-time performance, and is suitable for the acquisition of active images, but the circuit is more complex and the cost is high. The latter uses a general video A/D converter to realize image acquisition, and cannot complete automatic image acquisition. The entire acquisition process is completed under the control of the CPU. The CPU starts A/D conversion, reads A/D conversion data, and stores the data in the frame memory. Its characteristics are that data acquisition takes up CPU time and has high requirements on the processor speed, but the circuit is simple, low-cost, easy to implement, and can meet the needs of some image acquisition systems. The following takes TI's TMS320VC5402 (hereinafter referred to as C5402) DSP as an example to introduce the video image acquisition circuit and acquisition method based on the digital signal processor (DSP).

1 Circuit Principle

The acquisition circuit is shown in Figure 1, which consists of a video buffer, a video A/D converter, and a video synchronization separation circuit.

1.1 Video Buffer
The peak-to-peak amplitude of the standard black-and-white full-TV signal from the camera is 1V, which is sent to the A/D converter and the line and field synchronization separation circuit. The full scale of the A/D converter is 2V. Therefore, the video buffer must perform impedance matching and voltage amplification for the full-TV signal, and can adjust the black level of the full-TV signal. In Figure 1, U8 constitutes a video buffer with a gain of +2; the adjustment resistor W1 can adjust the DC level of the output signal; R16 is the input matching resistor, and the resistance value is determined by the signal source, which is 75Ω in this circuit.

1.2 A/D Converter

The A/D converter uses the TLC5510 chip from TI. The TLC5510 is a high-speed parallel A/D converter with a 5V power supply, 8 bits, and 20Msps, and the maximum range is 2V. The
reference voltage of the TLC5510 can be set by the three internal resistors R1, Rref, and R2, as shown in Figure 2. Connect as shown in Figure 2, set the reference low voltage to 0.6V, set the reference high voltage to 2.6V, and the 2V voltage drop on the resistor Rref is the range voltage. When the input voltage is 0.6V, the output data of the A/D conversion is 0; when the output voltage is 2.6V, the output data of the A/D conversion is 255.
The TLC5510 has 1 conversion clock input terminal (CLK) and 1 chip select terminal (OE). The falling edge of CLK starts the A/D conversion. One A/D conversion requires 2.5 CLK cycles. That is, after the falling edge of the first CLK starts the A/D conversion, the first A/D conversion data will not be ready until the rising edge of the third CLK appears. When the chip select signal (OE) is low, the A/D conversion data is output to the external data bus for DSP to read.

1.3 Connection of DSP in the acquisition circuit The
connection between the acquisition circuit and C5402 is shown in Figure 3. Among them, U19 is a 16-bit high-speed bus transceiver with a level conversion function, which converts the 5V odd and even field signal, reset synchronization signal and the digital signal output by the A/D converter into a 3.3V signal that C5402 can accept.

After carefully analyzing the working principle of TLC5510 and the read/write timing of C5402, TLC5510 is not used as an extended I/O port of C5402, but as an extended external storage unit of C5402. The read strobe signal (ADR) of this unit is connected to the CLK and OE of TLC5510 (as shown in Figure 3). In this way, when C5402 reads TLC5510, one read instruction completes two operations: starting A/D conversion and reading A/D conversion data. However, the current A/D conversion result can only be obtained when the port is read for the fourth time. The timing of A/D conversion is shown in Figure 4. The read strobe signal (ADR) is obtained by a high-speed decoder (74AHCT138) after a first-level decoding. This design simplifies the circuit, simplifies the program design of data acquisition, and reduces the time for DSP to participate in A/D conversion. Experiments have shown that this design has superior performance - the DSP only needs to read TLC5510 directly when collecting image data.

1.4 Synchronous separation circuit
The synchronous separation circuit uses LM1881. This device can receive full television signals of PAL, NTSC and SECAM systems, and output composite synchronization signals, vertical synchronization signals, odd and even field signals and color synchronization flag pulse signals. In this circuit, the composite synchronization signal is connected to the INT0 pin of C5402, and the odd and even field signals are connected to the input pin BIO of C5402 (as shown in Figure 3). C5402 finds the beginning of an image according to the odd and even field signals and prepares to collect image data. When the composite synchronization signal arrives, C5402 responds to the line interrupt (INT0) and continuously collects a line of image data.

2 Image Acquisition
The image acquisition of the compression card is directly completed by C5402. After initialization, C5402 determines the image size and acquisition rate and other parameters according to the default mode or host command, and then acquires image data according to the odd and even field signals and composite synchronization pulse signals.

2.1 Collection process
The collection process can be divided into the following steps:
① Wait for the field to start.
② When the field start signal arrives, C5402 enters the field processing subroutine, opens the line interrupt and prepares to collect a field of data. According to the odd and even field signals, it can be determined whether to collect odd field images or even field images, or collect a complete frame of images.
③ When the complex synchronization signal arrives, C5402 enters the interrupt service subroutine, continuously collects a line of image data, and stores the image data in the extended data memory. When all the lines of data for a field or a frame of image are collected, the interrupt is closed.

2.2 Line and field processing
After receiving the field start signal, the DSP enters the field processing subroutine. In the field processing subroutine, first determine the size of the image to be collected and set the parameters to be used in the collection, encoding and sending process, then turn on the line collection interrupt INT0, delay a certain number of line cycles and exit the field processing subroutine to enter the image collection stage.
The line collection interrupt must complete image collection and some other tasks. Between each line of image collection, a delay should be made for a period of time according to the image size to ensure that the collected image is located in the center of the screen. When collecting images, read an A/D conversion data every 140ns and store it in the frame buffer. Since it only takes 80ns to read the A/D conversion result and write the frame buffer, the image data can be subtracted by 128 before being stored in the frame memory. In this way, the subtraction operation of 128 does not need to be performed during JPEG encoding, saving time.

Conclusion
This circuit is low-cost, easy to implement, takes up little DSP time, and can meet the acquisition of black-and-white TV signals. It has been applied in the portable quasi-motion video image compression system developed by the DSP Joint Laboratory of Hefei University of Technology with good results. Based on this circuit, other high-speed video A/D converters from TI, such as TLC5540 or TLC5580, can form a higher-resolution video image acquisition system.