Multicore DSP implementations require intelligent power management given the plethora of voltage and current requirements for the core, memory, I/O, and other rails. An important performance benchmark for the DSP core voltage supply is the ability to adjust VCORE in real time based on DSP usage and environmental conditions. The VCORE command is typically provided in a digital format that the power supply should be able to interpret at all times. The VCORE rail typically has the largest current specification, and a small power solution that balances efficiency and size is also important. The key is to implement this voltage identification (VID) function using a low-cost interface between the DSP and the analog PWM stage. Therefore, the following figure provides an illustration of a multicore DSP with the core rail labeled as CVDD. I also published an article in EDN magazine titled “Optimizing DSP Power Budget by Adjusting Regulators” that explores this topic in depth. A 500KHz buck converter rated for 15A supplies power to CVDD. The design implements VID control using a 4-wire digital interface to a VID programmer, which can be directly connected to any analog power stage or controller. Click here to view a video demonstration of the VID programmer. Schematic diagram of a functional synchronous buck converter [color=r gb(85, 85, The LM10011[/url] not only captures the VID information presented on the DSP VCNTL interface, but also sets the current DAC output connected to the feedback (FB) pin of the power stage circuit. In 6-bit mode, 64 current settings with 940nA resolution are provided, while providing better than 1% error accuracy. In this example, CVDD is determined by the DSP to be a voltage level between 0.9V and 1.1V, supporting 6.4mV step resolution. Resistor RSET determines the CVDD voltage at startup without the need for level shifters or glue logic. LM10011 can be connected to any voltage, current or DCAP mode PWM regulator with FB input.
|