On the modeling and configuration of DSP systems

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On the modeling and configuration of DSP systems [Copy link]

Embedded software development requires extensive knowledge and understanding of the target architecture and its use. There are a series of steps required to transform an embedded system from concept to an efficient solution that can be effectively deployed in a hardware environment. The entire process includes: analysis, architecture construction, evaluation, hardware support, design, coding, debugging, integration, verification and validation. During this process, if the hardware resources are not used effectively or the software is not optimized for the hardware resources, performance may be seriously affected. The innovative architecture used in the CEVA-X series of DSP cores requires a completely new approach to fully utilize the possible design variables to control the overall performance. The CEVA-X1620 is the first product in the CEVA-X core family and adopts a very advanced parallel architecture that can execute up to 8 instructions in one machine cycle. For such advanced architectures, high performance and efficient use of hardware resources are very important. In addition, CEVA-X integrates a complete memory subsystem for hierarchical memory management. This includes direct memory access (DMA) controllers, on-board caches, write buffers, internal and external memory, memory management and arbitration. With this extensive feature set, optimization of software applications can be easily accomplished through a complete and accurate simulation environment and advanced configuration capabilities. Requirements for the Simulation Environment For DSP/real-time based software development, the simulation environment is very important and needs to have the following characteristics. Visibility Transparency - The operation of internal hardware and hardware logic can be monitored. Even though they are not part of the hardware interface and are generally not visible in the actual hardware environment, understanding their behavior is key to solving problems and improving performance. Debugging - When there is a lack of an accurate simulation environment, running all processes on hardware that only provides limited visibility means that more resources need to be utilized and debugging time will be increased. Therefore, the simulation environment should provide additional debugging capabilities not supported by the hardware itself. Flexibility - This refers to the ability to examine several different system layouts before committing to a final system architecture. Achieving optimal performance often involves setting different hardware environment parameters and performing trial and error with software. The simulation environment is relied upon to accurately predict the impact on the system of the specific settings chosen. Time - The development of hardware and software can be done in parallel without expending too much time and adding special hardware before all run-time testing can be performed. Accurate Simulation and Comprehensive Configuration Advanced simulation and configuration environments use complete software modeling and comprehensive configuration capabilities to help system architects and DSP software engineers better design their applications. This approach and environment significantly improves system performance and reduces development time accordingly. The comprehensive modeling environment means that the CEVA-X1620 implementation can be used in multiple modes for different development phases or purposes. Simulation The first supported mode in the tool is a basic Instruction Set Simulation (ISS) mode similar to standard simulation solutions. In this mode, each instruction is executed as an indivisible stage. This mode is very fast and convenient for software development. Cycle Accurate Simulation (CAS) is a more advanced simulation mode. In this mode, the architectural behavior including all pipeline stages is fully simulated. This mode is very important for full system simulation when doing accuracy checks or hardware verification, where the simulator can conveniently emulate the functionality of real hardware as a kernel module. In addition to the cycle accurate capability, the entire memory subsystem (MSS) is modeled, allowing the entire system to be simulated. This allows for realistic and accurate simulation as the software interacts with the hardware. This mode includes all MSS modules, so all memory hierarchies can be debugged, including caches, write buffers, internal/external memories. In addition, it is possible to analyze different memory layouts through simulation to observe memory accesses and conflicts during algorithm execution for each layout. Configuration In addition to the comprehensive simulation capabilities, CEVA also provides a C-level application and memory configurator. This configurator automatically analyzes the entire simulation environment. It provides full C-level configuration in basic ISS mode. It can effectively improve software performance by finding potential problems such as application cores, bottlenecks and the most expensive code lines. This is a very powerful tool to reduce the clock count of critical functions and the code size of non-critical functions. Application profiling is automatically performed on C functions without any code changes, and can also be used for assembly programs. Application profiling can then be performed based on the CAS and MSS simulators to get the true application performance based on the memory map and memory conflicts of each function. Once the application has been configured in CAS and MSS mode and the functions have been identified, the configurator can give complete memory usage information including cache usage and conflicts, stall summary for each function, code memory stalls, data memory stalls, code memory conflicts and data memory conflicts. This comprehensive MSS profiling information guides the user to optimize memory usage for each specific function in the application. This modeling and profiling flow has been successfully used to achieve code reduction for certain computing functions and has helped to achieve excellent performance on many chipsets that have been finalized with CEVA cores.