Data conversion is accomplished by a 24-bit Σ-Δ analog-to-digital converter (ADC) AD7173-8 . The AD7173-8 is software configurable, allowing 8 fully differential or 16 single-ended input channels, providing great flexibility through a built-in crossbar multiplexer. The AD7173-8 is available in a small 6 mm × 6 mm LFCSP package, making it an ideal choice for applications where space is limited. An internal clock and precision 2.5 V voltage reference reduce external components, further saving space. Four programmable general-purpose output pins (GPIO0, GPIO1, GPO2, GPO3) allow control of an external multiplexer, thus switching multiple HART interfaces, thereby reducing additional wiring from the processor/controller. The AD7173-8 has internal calibration registers that can be programmed to provide offset and gain calibration on the full input path.

The AD5700-1 is the industry's lowest power, smallest package, HART-compatible modem, and together with the current input channels form a HART-compatible, 4 mA to 20 mA receiver solution. The AD5700-1 includes an internal precision oscillator for additional space savings, especially in isolation applications. The

ADG704 multiplexer provides connections between multiple current input channels and HART.

The ADuM5211 isolates the two data channels (Tx, Rx) and provides 5 V supply isolation through integrated isoPower® technology. The ADuM3151 PIsolator provides serial peripheral interface (SPI) isolation at clock rates up to 17 MHz (Class B) while isolating three additional data channels.

The ADP2441 is a 36 V, step-down regulator that accepts industry-standard 24 V supplies and has a wide input voltage. The ADP2441 reduces the input voltage to 5 V to power all controller-side circuitry. The circuit also includes peripheral protection on the standard 24 V input.

 

Figure 1. PLC/DCS four-channel voltage and current input front end (simplified schematic: all connections and decoupling circuits are not shown)

Voltage Input Circuit

Figure 2 shows the voltage input network for Channel 1. 

Current Input Circuit

Figure 3 shows the current input network for Channel 1.

 

Figure 3. Current input equivalent circuit (simplified)

 
This circuit has four channels of current inputs and supports a maximum input range of 0 mA to 24 mA. The input impedance of the circuit is 250 Ω, and the input reference is ground. A 100 Ω precision current sense resistor is used, so the 24 mA input produces 2.4 V, which is within the 2.5 V input range of the AD7173-8 (using the internal 2.5 V voltage reference). The evaluation board has a default installed resistor of 0.1%, 10 ppm/°C.

The ADC input is divided into two input paths. The fast input path is used for channels that do not use HART, and the slow input path is used for channels that use HART.

The fast input path allows the full bandwidth of the Σ-Δ ADC signal input. It is also possible to use an internal sinc filter to filter out the HART frequencies of 1.2 kHz and 2.2 kHz. However, using the sinc filter requires running the relevant channels at 400 SPS data rate (sinc3 filter screening), which will increase the conversion time required for all four channels.

The slow input channel contains a 16 Hz two-pole filter that filters out the 1.2 kHz and 2.2 kHz HART digital signal frequencies. Using this input, the Σ-Δ ADC can still operate at fast data rates while filtering out the HART digital signal frequencies. There is no increase in conversion time for all four channels. ADC operation at fast data rates is especially useful if HART is not enabled on all channels.

Current input line parameters are summarized in Table 2.

Table 2. Current input line parameters (maximum values ​​based on worst-case calculations)

parameter	numerical value	unit	Test conditions/comments
input resistance	250	Ω	ground
Error due to resistance	N/A 1	%FSRmax	Specifications for each R SENSE resistor
Error due to resistor drift	N/A 1	ppm/°C max	Specifications for each R SENSE resistor
Error due to baseline drift	10	ppm/°C max	internal benchmark
data rate	31.25 1.55 6.25	kSPS kSPS SPS	Enable 1 input (14.8 bits of noise-free coding resolution for 0 mA to 20 mA) 4 channels, fully stable per channel, sinc5+1 filtering (14.8 bits of peak-to-peak resolution for 0 mA to 20 mA ) 4 channels, fully stable per channel, 50 Hz/60 Hz rejection (18.1 bits peak-to-peak resolution for 0 mA to 20 mA)
input filter	27 16	kHz Hz	Fast input provides HART filtered low-speed input

¹ N/A = Not applicable


HART input and output circuits

Figure 4 shows the HART input and output circuits.

Figure 4. HART input and output circuit (simplified)

The function of HART is to multiplex among four current input channels. Through two ADG704 multiplexers (SW1 and SW2 in Figure 4), the HART input and output networks are shared on four channels.

The HART input circuit consists of a HART bandpass filter composed of R3, C1, C2, R4, and R5. The AD5700-1 data sheet has a description of this filter. Each channel uses a switch (SW1) to switch the HART input line to the HART active channel. There is a 150 kΩ resistor (R3) on each channel, which is part of the bandpass filter and provides additional protection for switch SW1. The HART input is connected directly to the current input to ensure that the ADC_IP pin of the AD5700-1 receives the correct voltage level.

Each channel uses a switch SW2 to switch the HART output line to the active channel. Capacitor C3 is used to couple the HART signal. The combination of R1, C3, R6, and R7 needs to be carefully selected to ensure that the voltage at the HART_OUT pin of the AD5700-1 is within a 25 Hz, 4 mA to 20 mA input signal (for a HART enabled device, represents the fastest allowable rate ) is not lower than GND.

Figure 5. Power supply circuit (simplified schematic: not all connections shown)

 

Power Supply Circuit

The evaluation board is powered from a 5.5 V to 36 V DC supply and uses an on-board switching regulator to provide 5 V to the system, as shown in Figure 5. In the test setup, 5 V powers the EVAL-SDP-CB1Z Demonstration Platform (SDP) evaluation board. The EVAL-SDP-CB1ZSDP board provides VIO's 3.3V voltage. The high switching frequency of the ADP2441 provides minimal output voltage ripple

even when using a small inductor sizeThe choice of inductor size requires a trade-off between efficiency and transient response. A small inductor will cause a large inductor current ripple, which can provide good transient response, but the efficiency will be reduced. Due to the high switching frequency of the ADP2441, it is recommended to use shielded ferrite core inductors because they have low core losses and low electromagnetic interference (EMI). In the circuit of Figure 5, the switching frequency is approximately 1 MHz and is set by an 88.7 kΩ external resistor. The 12 μH inductor (Coilcraft LPS6235-123MLC) was selected according to Table 8 of the ADP2441 data sheet. The circuit is connected to a 5.5 V to 36 V power supply via screw terminals. The EARTH terminal can be connected to the external earth, and is always connected to the GND terminal when external grounding is not used. A power inductor (DR73-102-R), varistor (V56ZA3P, 56 V), power diode (S2A-TP, 50 V) and a 1.1 A fuse provide additional input voltage transient protection.

Noise test:

Short-circuit the input terminals of each channel to evaluate the system noise. This will make the differential voltage of each input channel zero and the input of each current input channel be grounded. Data is collected when the input is short-circuited, and the code distribution and noise-free coding resolution are calculated from the number of samples.Noise testing

can be performed using the CN-0364 evaluation software . The distribution of each channel code and the noise-free coding resolution can be obtained, and the data is displayed in a histogram. The histogram in Figure 6 is sample data collected from the Channel 1 voltage input.

Figure 6. Channel 1 voltage input, input shorted, biased to reference voltage, 31.25 kSPS, Sinc5+1 filter, 2000 samples (15.8-bit noise-free encoding resolution)

HART test

The HART function is tested in accordance with the HART physical layer test specification (HCF-Test-2). This circuit meets the requirements of the HART physical layer. More details on the HART specifications can be obtained directly from the HART Communications Foundation.

The ADC input was tested for rejection of HART 1.2 KHz and 2.2 KHz signals. Table 3 shows the test results.

Table 3. Suppression of 1.2KHz and 2.2 KHz HART Frequencies

operating mode	Frequency(kHz)	Suppression(dB)
Low speed input path, 31 kSPS Sinc5+1 filtered	1.2 2.2	60.5 66.5
Fast input path, 400 SPS Sinc3 filtering	1.2 2.2	≥74.4 66.6

A complete design support package for the EVAL-CN0364-SDPZ evaluation board, including schematics, BOM and layout, can be downloaded from www.analog.com/CN0364-DesignSupport .