This post was last edited by lvxinn2006 on 2019-1-11 08:55 The development board evaluated in this eventST NUCLEO-G071RB is provided by STMicroelectronics. Thanks to STMicroelectronics for its support for EEWorld's evaluation!
【Purpose】
· Master the use of serial port
· Master the configuration of system clock
· Master the implementation logic of Tetris game
【Experimental environment】
· NUCLEO-G071RB development board · Keil MDK-ARM (Keil uVision 5.25.2.0) · Keil.STM32G0xx_DFP.1.0.0.pack · MobaXterm, Putty, SecureCRT, XShell and other hyperterminal software.5pt] 【Experimental Materials】
· NUCLEO-G071RB Development Board Schematic Diagram
· STM32G071x8/xB Data Sheet
·STM32G071 chip user reference manual
[ExperimentAnalysis]
Based on the previousUART serial port experiment, the functional logic of Tetris is added. It contains many C language algorithms and the use of terminal control codes. The content is relatively complicated. The program code is provided here for interested readers to refer to.
In this experiment, two additional processor functions are mainly used
1. Configuration of main system clock increased to 64MHz
2. Use of Systick beat timer
The configuration of 64MHz main clock mainly uses the RCC unit of the chip. The RCC unit is mainly used to control the reset and clock control of each functional unit of the entire chip system. Here, clock control is mainly used.
The basis of clock control mainly depends on the system clock tree. The part related to the system main frequency is shown in the following figure:
[attach]398003 [/attach]
In fact, it is necessary to make SYSCLK The clock frequency reaches 64MHz through various settings. According to the clock diagram and the chip manual, we can know that the system uses the internal 16MHz RC oscillation circuit as the clock by default, that is, HSI16, and after the divider (undivided by default), it becomes HSISYS. The main clock SYSCLK selector selects HSISYS as the main clock source by default, and the default main clock SYSCLK frequency is 16MHz. According to the understanding of the STM32G071 chip, the maximum supported frequency of the SYSCLK master clock is 64MHz. As the main clock of the system, SYSCLK provides the clock source for the CPU core and most peripheral devices. This chip uses the Cortex-M0+ CPU core of the architecture, with HCLK as the working clock, and the maximum main frequency can run to 64MHz. In summary, if we want to maximize the performance of the processor, we need to increase SYSCLK to the maximum supported frequency of 64MHz. In the clock part, there is a PLL component in the system. Its main function is to increase the clock frequency, input a low-frequency clock signal, and output a high-frequency clock signal. As can be seen in the figure, PLL can choose HSE or HSI16 as the clock source. In our development board, only HSI16 can be used, so this part needs to be configured separately. The entire PLL related configuration is in register [ In PLLCFGR: 398004 398005 398006 In this register, we are mainly concerned about several values M, N, P, Q and R. Combined with the clock tree and the register formula description, we can clearly understand the role of each bit segment. The two most important parameters here are M and N. These two determine the frequency of fvco inside the phase-locked loop PLL. The three output clocks are divided based on this frequency, so it is necessary to select reasonable values for M and N. After configuring the PLL parameters, you need to start the PLL, which mainly uses the RCC_CR register.
needs to turn on the 24th bit, and needs to detect whether the PLL is working properly by testing the 25th bit. After everything is normal, you can switch the SYSCLK clock source to PLLRCLK. The selection of the main clock source mainly uses RCC_CFGR398007398008. Set 2:0=010 (0x2) here to select the main clock as PLLRCLK. After the clock is switched successfully, you can verify whether the clock is switched successfully by reading 5:3. /font]
To summarize, the clock configuration function is implemented as follows:
- /* Configure 64MHz system clock*/ void SystemClockConfig(void) { //Fvco1 = 16 * 32 / 4 = 128 RCC->PLLCFGR = (0x2<<0) //PLL clock source select HSI16 | (4<<4) //M=4 | (32<<8) //N=32 | (1<<28) //Enable PLLRCLK | (1<<29); //R=1 PLLRCLK division coefficient is 2, then PLLRCLK frequency is 64MHz RCC->CR |= (1<<24); //Enable PLL while(!(RCC->CR & (1<<25))); //Wait for PLL to lock RCC->CFGR |= (0x2<<0); //Switch clock source to PLLRCLK while(!(RCC->CFGR & (0x2<<3))); //Wait for the clock source switching to complete SystemCoreClockUpdate(); //Update the SystemCoreClock global variable }
Running this function in the main function can increase the main clock frequency to64MHz, and you can get the currentSYSCLKclock frequency by accessing the global variableSystemCoreClock.
Experimental code]
[Experimental phenomenon]
· Connect the development board, open the HyperTerminal software, and use the baud rate of115200 to connect to the serial port of the development board (Note: only the HyperTerminal software can be used, the Serial Debug Assistant cannot be used. The Serial Debug Assistant can only see the original terminal control code)
· Start the game after the development board is reset, and use the keyboard keys to control the direction
S ——Left
D ——Down
F ——Right
E ——Switch direction
Space bar pauses/Continue the game
R ——Restart
The terminal displays the following:
This content is originally created by EEWORLD forum user lvxinn2006. If you want to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source(RCC->CFGR & (0x2<<3))); //Wait for the clock source switching to complete SystemCoreClockUpdate(); //Update the SystemCoreClock global variable }[/code]
Running this function in the main function can increase the main clock frequency to64MHz, and you can get the currentSYSCLKclock frequency by accessing the global variableSystemCoreClock.
Experimental code]
[Experimental phenomenon]
· Connect the development board, open the HyperTerminal software, and use the baud rate of115200 to connect to the serial port of the development board (Note: only the HyperTerminal software can be used, the Serial Debug Assistant cannot be used. The Serial Debug Assistant can only see the original terminal control code)
· Start the game after the development board is reset, and use the keyboard keys to control the direction
S ——Left
D ——Down
F ——Right
E ——Switch direction
Space bar pause/Continue the game
R ——Restart
The terminal displays the following:
This content is originally created by EEWORLD forum user lvxinn2006. If you want to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source
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