• You can log in to your eeworld account to continue watching:
  • SDK Bare Metal Development - AXI DMA AN9767 Signal Generator Vitis Project
  • Login
  • Duration:14 minutes and 17 seconds
  • Date:2024/12/16
  • Uploader:Lemontree
Introduction
keywords: FPGA
This set of video tutorials is an original video tutorial by ALINX based on Xilinx Zynq UltraScale+ MPSoC series FPGA. The content includes five parts: bare metal development, Linux basic development, Linux driver development, Vitis HLS development, and Vitis AI development. It details the development content of each part of the MPSoc series FPGA chip. The video is based on the FPGA development board independently designed by ALINX. It combines theory with practice so that everyone can fully understand the development ideas. At the same time, it is close to the project and demonstrates mainstream technologies, such as the application of artificial intelligence AI, vehicle recognition, pedestrian detection, PCB defect detection, construction site safety helmet detection, flame detection, office target recognition, thermal imaging ADAS vehicle detection, concrete defect detection, etc., giving full play to the flexibility, high performance, low latency, high reliability and other characteristics of the MPSoc series FPGA chips.
Unfold ↓

You Might Like

Recommended Posts

Application of Cluster Communication Technology in GPS Vehicle Monitoring System
Abstract: This paper introduces the communication mode of GPS vehicle monitoring system. Based on the introduction of cluster system, this paper focuses on the application of cluster communication tec
frozenviolet Automotive Electronics
Commonly used software for microwave engineering
1: HP ADS ***** is powerful, and is very powerful in communication system simulation and microwave circuit simulation. It has a slightly weaker layout calculation function, with MOM, finite element, b
JasonYoo RF/Wirelessly
GCC GD32E230 toolchain startup and linking files
Share the GD32E230 GNU Tools for Arm Embedded Processors tool chain startup and connection files.
serialworld GD32 MCU
Top 10 Algorithms Every Machine Learning Engineer Must Know
[i=s] This post was last edited by Bai Ding on 2017-7-23 10:53 [/i] [size=4][url=http://www.infoq.com/cn/articles/10-algorithms-machine-learning-engineers-need-to-know]Original address [/url] [color=#
白丁 FPGA/CPLD
High-speed ADCs: Preventing front-end conflicts
Author: Joshua Israelsohn Source: EDN China Trends in end applications show that OEMs are still pursuing higher speed and resolution, lower distortion, loss, smaller size and lower cost. But converter
fighting Analogue and Mixed Signal
Power saving with DPM
The defining characteristic of DPM is the rapid, high-frequency nature of power management. Unlike the traditional desktop/laptop paradigm, which operates in hundreds of milliseconds or seconds, DPM e
zbz0529 Power technology

Recommended Content

可能感兴趣器件

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews


Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号