I didn't expect the competition to end so soon. I really feel unwilling to give up. There are gains and regrets in the process. Gains: 1. The functions of reading and displaying the pulse signal on th
The reason for dividing into digital ground and analog ground
Since digital signals are generally rectangular waves with a large number of harmonics, if the digital ground and analog ground in the cir
I don't use a clock chip. I use a digital tube. The problem I encounter is that when the digit is carried from a low position to a high position, how can I keep the high-bit digit from being destroyed
Now we use 8g08 nand. The previous FMD+FAL driver is not usable and is very unstable. We use the driver written by the agent before, but there are also problems, but the probability is smaller. I see
[i=s]This post was last edited by Jingfengzi on 2021-3-25 14:20[/i]The FPGA chip model I am using now is EP4CE15F17C8, and the FPGA input clock frequency is 50 MHz. According to the official routine,