Location:Training / Tools/EDA / IC Design and Methods / Verilog syntax for testing (1)

Integrated circuits are one of the essential components of modern electronic systems. The design process of digital integrated circuits includes front-end design and back-end design. In the front-end design stage, on the basis of completing the digital system architecture and algorithm design, the main design is Register Transfer Level (RTL) code, and logic synthesis generates a gate-level netlist; the back-end design includes layout planning, standards Brick unit placement and routing, layout generation and inspection, etc.
This course introduces the IC design process and design methods, basic knowledge of VHDL and Verilog languages, simulation tools, basic concepts of synthesis and tool usage.