First 6nm RF process, US wafer fab started

According to Jiwei.com, today (2), TSMC held an online technology forum, revealing the latest innovations in advanced logic technology, special technology, and 3DFabric advanced packaging and chip stacking technology. So what important information did TSMC reveal?

TSMC's wafer foundry technology has always been at the forefront of the industry. Today, TSMC released its 6nm RF (N6RF) process for the first time, bringing the power consumption, performance, and area advantages of the advanced 6nm logic process to 5G RF and WiFi 6/6e solutions. It is reported that compared with the previous generation of 16nm RF technology, the performance of N6RF transistors has increased by more than 16%.

TSMC said that the N6RF process provides significantly reduced power consumption and area for 5G RF transceivers below 6GHz and in the millimeter wave frequency bands, while taking into account the performance, functionality and battery life required by consumers. It will also enhance the performance and power efficiency of supporting WiFi 6/6e.

5nm process technology led the industry in mass production in 2020, and has now exceeded 500,000 wafers. TSMC pointed out that in response to strong customer demand, the production capacity of the 5nm series process, including 4nm, will increase by more than 4 times in 2023 compared to 2020.

The development of 4nm process technology is progressing smoothly, and trial production is expected to begin in the third quarter of 2021, one quarter earlier than the original plan for trial production in the fourth quarter of 2021. Yuan Liben, director of TSMC's advanced technology business development department, pointed out that low-end mobile phones, consumer electronics, mobile base stations and networking products need to consider costs, so the time for these products to adopt the most advanced process technology will be slightly delayed. Currently, most products use 16/12nm and are moving towards 6nm. It is believed that by 2023, the mainstream technology used by these products will be 4nm.

The 3nm process technology will be mass-produced in the second half of 2022 as originally planned, and will become the world's most advanced logic technology by then. Compared with the 5nm process technology, the 3nm process is 15% faster, consumes 30% less power, and increases logic density by 70%.

In addition, TSMC will also build a new wafer factory in Hsinchu as a 2nm production base, and the land acquisition process is currently underway.

At the same time, TSMC continues to promote advanced packaging and plans to have five plants in advanced packaging by 2022. TSMC has integrated related technologies into the "3DFabric" platform, incorporating all 3D advanced packaging technologies including the Integrated Fan-Out (InFO) family, CoWoS (Chip on Wafer on Substrate), and other chip stacking solutions such as SoIC.

As early as the end of last year, there was news that TSMC would build a wafer factory in Phoenix, Arizona, USA. Today, TSMC President Wei Zhejia mentioned that the company has invested 12 billion US dollars to build a 12-inch wafer factory in Arizona. Construction has already started and the project is progressing smoothly.

In addition, TSMC's senior vice president of operations, Qin Yongpei, also pointed out that the US plant is located north of the Phoenix Airport in Arizona, and the first phase is under construction. It is expected to use 5nm mass production chips in 2024, with a monthly production capacity of 20,000 pieces. According to the video played on the scene, TSMC's US plant covers an area of ​​1,100 acres (equivalent to about 445 hectares), which is more than the total area of ​​its Taiwan plant and more than half the area of ​​Taiwan Province's Hsinchu Science Park.