JEFA Technology's new patent improves clock skew in low voltage differential signal transmitters

According to Jiwei.com, NavInfo recently announced that its wholly-owned subsidiary Hefei JieFa Technology Co., Ltd. has obtained an invention patent certificate issued by the United States Patent and Trademark Office. The solution in this patent effectively improves JieFa Technology's technical barriers in data transmission quality and sampling accuracy of the vehicle-mounted low-voltage differential signal (LVDS) interface.

At present, since low voltage differential signals can reduce electromagnetic radiation and improve anti-interference capabilities, and serial can save signal lines, the interface of the liquid crystal display (LCD) used in vehicles is mainly LVDS interface.

In the prior art, two phase-locked loops (PLLs) are used to implement the LVDS interface, which respectively use the system PLL and the internal PLL of the port physical layer chip (Phy) to generate clock signals. The pixel clock signal needs to be processed by the internal PLL, and the data signal is processed by the parallel input serial output module in the Phy chip. Therefore, the paths of the data signal and the pixel clock signal are different.

Such a design scheme makes it easy for the output clock signal and data signal to have a phase difference, which is poor in synchronization alignment. This is mainly reflected in the poor clock offset parameters, especially for dual links. The poor synchronization also limits the tracking ability of the clock signal after spread spectrum.

Therefore, on May 8, 2019, Jiefa Technology applied for an invention patent entitled "A low-voltage differential signal transmitter and data transmission device" (application number: 201910381532.7), and the applicant was Hefei Jiefa Technology Co., Ltd.

Based on the relevant information currently disclosed in the patent, let us take a look at this low-voltage differential signal transmitter solution.

As shown in the figure above, it is a structural diagram of the low-voltage differential signal transmitter invented in this patent. The transmitter mainly includes a controller 11 and a physical layer chip 12. The controller is used to receive a first clock signal, and process the first clock signal to obtain a second clock signal, read the first data signal under the drive of the second clock signal, and output a third clock signal and a second clock signal.

The physical layer chip is connected to the controller, and is used to receive the first clock signal and the signal output by the controller, and use the first clock signal to sample and process the third clock signal and the second data signal, and output serial low-voltage differential clock signal and data signal, and the phase difference between the two signals will be controlled within a preset range.

Afterwards, the solution uses a phase-locked loop to generate a clock signal, and samples and outputs the third clock signal output by the controller as a special data channel. Driven by the first clock signal, the physical layer chip is used to process the third clock and second data signals output by the controller to ensure the synchronization of the data signal and the clock signal and improve the clock offset index. The specific low-voltage differential signal transmitter is shown in the figure below.

As shown in the figure above, the first clock signal is a sampling clock signal, which can perform spread spectrum processing on the preset clock signal; the second clock signal is a pixel clock signal; the third clock signal has the same frequency and duty cycle as the serial low-voltage differential clock signal, and its signal is a constant clock string. For a single link, one constant clock string is required, and for multiple links, multiple constant clock strings are required.

The first data signal is a signal output by an external graphics processor, including data signals of three channels of RGB. For example, the controller can map the RGB data set output by the previous graphics processor to meet the requirements of the LVDS format, and can also implement debugging functions such as signal line switching.

As shown in the figure above, it is a timing diagram corresponding to the circuit. The pixel clock signal CLK is used for the buffer inside the controller to read the first data signal from the front-end graphics processor. When the buffer stores the first data signal, the effective output signal val is a high level.

When the valid output signal val is at a high level and the data in one pixel clock has been stable for three sampling clock cycles, the load signal Load is pulled high and lasts for one sampling clock cycle. In this way, there will be a falling edge of the load signal Load in each subsequent pixel clock cycle, which can be used to latch parallel data.

The above is the low voltage differential signal transmitter invented by Jiefa Technology. This solution uses the physical layer chip to process and output the signal, so that the phase difference between the serial low voltage differential data signal and the serial low voltage differential clock signal meets the requirements, ensuring the synchronization of the data signal and the clock signal and improving the clock offset. Since only one phase-locked loop is used to generate the clock signal, the design of the overall solution can also be simplified, saving the cost of hardware resources.