Decoding the layout strategy for integrated circuit layout design registration

On January 25, the National Intellectual Property Administration released data showing that in 2020, my country issued 11,727 integrated circuit layout design certificates, a year-on-year increase of 77.3%. The number of companies that submitted applications for integrated circuit layout design registration reached more than 5,600, more than twice the number of the previous year. What strategies should be adopted for the layout of integrated circuit layout design registration?

In China, as a key industry to solve bottleneck areas, coupled with the recent hot topic of intellectual property, the intellectual property issues related to integrated circuits are particularly active. As mentioned in the author's previous article (Trade secrets or patents? Taking memory chips as an example to explain the layout strategy of chip intellectual property), in addition to patents and technical secrets, integrated circuit layout design registration as a unique intellectual property protection method for integrated circuits has received more and more attention in China.

The increase and decrease of integrated circuit layout design registration

Figure 1 below is a trend chart of the number of domestic integrated circuit layout design registration applications since 2001. It can be seen that the number of applications has basically increased year by year, especially after 2016, when it rose sharply.

figure 1

According to the data from 2020, my country received 8,319 applications for integrated circuit layout design registration in 2019, a substantial increase of 87.7% compared to 4,431 in 2018! On January 25, the National Intellectual Property Administration released data showing that in 2020, my country issued 11,727 integrated circuit layout design certificates, a year-on-year increase of 77.3%. The number of companies that submitted applications for integrated circuit layout design registration reached more than 5,600, more than twice the number of the previous year!

But what is the situation of integrated circuit layout design registration in countries with relatively mature industries? The following Figure 2 is a trend chart of the number of integrated circuit layout design registration applications in the United States and Japan. It can be found that the situation in the United States and Japan is very different from that in China. Since the end of the 1990s or even earlier, the number of integrated circuit layout design registration applications in the United States and Japan has gradually decreased. After 2010, the number in Japan even dropped to single digits, and the number in the United States has gradually dropped to about a few dozen.

figure 2

The large-scale application of EDA tools makes it difficult to reproduce the art of layout

What are the reasons for the above phenomenon? In fact, we can get a glimpse of it by analyzing it from the perspective of technology and intellectual property rights.

As mentioned above, from a technical perspective, as technology develops, the integration of chips becomes higher and higher, and more and more functions and devices are integrated into one chip. The design of integrated circuit layout tends to adopt automatic layout and routing (APR) design using computer-aided tools (EDA tools), especially for digital circuits that are becoming mainstream. Since it is designed automatically by machines, it is difficult to call it "art"; even analog circuits, which are more likely to be considered "art", are gradually mixed with more digital circuits, and gradually tend to be mixed analog and digital circuits or chips, so that the automatic layout and routing design of analog integrated circuits has become a hot topic and direction for more discussion in the industry.

For intellectual property rights, the most important feature is the ability to effectively protect the rights of all. At the same time, tens of millions to hundreds of billions of devices are integrated into one chip. It is difficult for such a huge scale of layout design to reflect the "artistic" side, and it is difficult to simply and effectively determine whether it has been infringed. Therefore, it is difficult to effectively protect and defend rights through integrated circuit layout design registration.

The author consulted the "Annual Report on Intellectual Property Cases of the Supreme People's Court" in recent years and found that the Intellectual Property Court of the Supreme People's Court has received more than 1,000 cases each year, but there are only a few cases involving integrated circuit layout designs each year, and even none in some years. The scarcity of integrated circuit layout design litigation cases may reflect the difficulty of integrated circuit layout design registration for all protection. From some typical cases (such as the integrated layout design case in the top ten typical cases of Shanghai Intellectual Property in 2014), it can be seen that even if the litigation procedure is entered, the infringement determination process also requires very complicated professional knowledge identification and argumentation process. It can be seen that the protection and protection of integrated circuit layout design registration is quite difficult. This also indirectly explains why the number of integrated circuit layout design registrations in relatively mature countries such as the United States and Japan is decreasing; on the contrary, in China, it may just indicate that the domestic chip industry is in a stage of catching up.

Four major processing strategies for integrated circuit layout design registration

Since it is difficult to protect the rights of the registered owners of integrated circuit layout designs and there are many difficulties, does it mean that the registration of integrated circuit layout designs is meaningless? The answer to this is of course no. In order to better play the role of integrated circuit layout design registration, necessary strategies and methods are needed when applying for registration.

Below, based on the author’s experience in chip R&D and design and his work in intellectual property, I would like to discuss some coping strategies for the above-mentioned dilemma.

First, focus on local protection

Nowadays, the scale of chips is getting bigger and bigger, and the number of devices and functions included is increasing. It is very difficult to apply for protection through layout design of the overall layout (Floor Plan) of the chip. Therefore, we should focus on local protection, that is, to protect the module area that can reflect the circuit function and original design separately or in a focused manner.

As stipulated in the Regulations on the Protection of Integrated Circuit Layout Designs, "a protected layout design shall be original, that is, the layout design is the result of the creator's own intellectual labor, and at the time of its creation, the layout design is not a recognized conventional design among layout design creators and integrated circuit manufacturers."

Protecting the key module areas in the chip can not only protect the key modules in the chip layout design, but also make it easier to collect evidence and make identifications when judging infringement. Of course, if it is a chip with a very small area and scale, such as an analog circuit with simple functions, the entire chip layout design should still be protected.

Secondly, use combined protection

The combined protection mentioned here refers to the flexible registration of integrated circuit layout design and invention or utility model patents based on the characteristics of the innovative and improved parts of the designed integrated circuit layout. For example, some smaller local layouts, combined layouts of single or simple devices, etc., are more suitable for combined protection. Because the format and content of the patent (the way the claims are described, the explanation of the specification, etc.) the layout form of the integrated circuit with a multi-layer structure may not be clearly defined and protected; while the registration of integrated circuit layout design can make good use of the graphic filing to relatively accurately define the corresponding graphic structure. For example, the word line structure (open word line Open-bitline, folded word line Folded-bitline) in the DRAM memory storage array, the structure of the three-dimensional storage unit in the NAND flash memory, the PN junction layout structure that generates a negative temperature coefficient voltage in the bandgap reference voltage module, etc. It should be noted that the creativity of the combined layout of such simple devices is often not high, so it may be more appropriate to protect it through combined utility model patents.

For example, in the Apple-Qualcomm series of invention patent invalidation cases, which were among the top ten patent reexamination invalidation cases released by the State Intellectual Property Office in 2018, Qualcomm's patent "ZL201480013124.1 Circuit with high-density local interconnection structure and its manufacturing method" involves integrated circuit multi-layer metal interconnection structure in deep submicron process nodes. This patent is an improvement on the layout of simple device combinations. If this patent can be applied for integrated circuit layout design registration at the same time, it should play a more stringent and complete protection role for the right owner of this technology (Qualcomm).

Again, suitability registration

Because when applying for integrated circuit layout design registration, you need to provide pattern images of different layers of the chip layout. The patterns of these layers will eventually be made into corresponding masks, and then the photolithography machine will use these masks to process the silicon wafers and finally manufacture the key information of the chip. When applying for the above, it is also necessary to explain and introduce the processes of different layers. To a certain extent, this information is also the key technical information of major chip manufacturers (such as TSMC, Samsung, SMIC, etc.). The provision of this information may involve the risk of technical secrets being leaked. Therefore, in order to reasonably apply for protection of integrated circuit layout design registration and avoid the risk of technical secrets being leaked, you can make trade-offs in the provision of different layers.