Zhicun Technology reveals the secrets of digital-analog hybrid storage and computing chip

Recently, Zhicun Technology completed its A+ round of investment. It is reported that this investment will support Zhicun Technology to increase its R&D efforts and expand its business capabilities in the field of artificial intelligence edge chips. This is also another important strategic investment by Guotou in the cutting-edge field of artificial intelligence chips.

Zhicun Technology was founded in October 2017 and is headquartered in Haidian District, Beijing. Its founding team was the first in the world to use Flash to build a deep learning neural network based on a storage-computing integrated architecture, and completed the world's first "storage-computing integrated" deep learning chip.

In recent years, the integrated computing chip architecture has received extensive attention and research. This chip transforms the traditional computing-centric architecture into a data-centric architecture, using memory for direct data processing, thereby integrating data storage and computing in the same chip. It effectively completes convolution operations through simulation, breaking through the traditional von Neumann architecture, and thus has orders of magnitude improvement in power consumption and computing power compared to traditional chips.

The basic idea of ​​the traditional integrated memory and computing chip architecture is to embed logical computing units in the memory, so that some simple but large-scale logical computing functions can be completed in the memory, thereby reducing the amount of data transmitted and the transmission distance between the memory and the processor. However, the design complexity and manufacturing cost of embedding logical computing units in the memory are very high, making it difficult to industrialize on a large scale.

To this end, Zhicun Technology applied for an invention patent entitled "A digital-analog hybrid storage and computing integrated chip and computing device" on November 28, 2018 (application number: 201811436971.5), and the applicant was Beijing Zhicun Technology Co., Ltd.

Based on the information currently disclosed in the patent, let us take a look at this hybrid digital and analog storage and computing chip.

As shown above, this is the overall architecture of this digital-analog hybrid storage and computing chip, which includes multiple flash processor arrays and on-chip memory connected to these arrays. Each flash processing array reads the data in the on-chip memory, performs operations on the data, obtains the operation structure, and transmits the results to the on-chip memory, which finally stores the processing results.

Although the architecture contains multiple flash memory processing arrays, not all of them are used at once for data processing. Instead, they can be dynamically allocated on demand, which not only maximizes the utilization of the processing arrays but also significantly reduces the power consumption of the entire system.

In addition, the digital-analog hybrid computing chip provided by the patent can be integrated on an on-chip memory to realize the functions of digital-analog hybrid storage and computing, and can effectively reduce the design complexity and manufacturing costs, which is conducive to large-scale industrialization.

Next, let's take a look at the partial circuit structure diagram of this digital-analog hybrid storage and computing integrated chip. As shown in the figure above, based on the digital-analog hybrid storage and computing integrated chip, the structure also includes: write circuit 5, read circuit 6, DAC7, and ADC4.

The output end of the flash memory processing array is connected to ADC4, writing circuit 5, and on-chip memory 3 in sequence. Since the operation result output by the flash memory processing array is analog data, ADC4 is connected to the output end of the flash memory processing array to convert the analog operation result into a digital signal that can be stored in the on-chip memory. The digital signal is written into a predetermined address of the on-chip memory through the writing circuit, thereby realizing the use of digital memory to store analog data.

It is worth mentioning that the multiple flash memory processing arrays in the digital-analog hybrid storage and computing integrated chip share a set of ADC, DAC, write circuit and read circuit to interact with the on-chip memory. Because the on-chip memory is time-division multiplexed, multiple flash memory processing arrays share a set of ADC, DAC, write circuit and read circuit without affecting the chip function, and can also simplify the chip structure, reduce the chip area, and reduce the chip cost.

Then let's combine the neural network algorithms in practical applications to see how this hybrid digital and analog storage and computing chip can implement specific neural network algorithms.

As shown in the figure above, this is the current mainstream deep learning neural network structure diagram. The deep neural network includes t layers, namely Layer1~Layer(t). Each layer includes multiple neurons. Each neuron receives the output of multiple neurons in the previous layer as input, performs certain operations on the received data, obtains the output of the neuron, and inputs it to multiple neurons in the next layer as the input of the corresponding neurons in the next layer. Through gradual and progressive learning between multiple layers, complex operation recognition and other functions are realized.

Among them, Layer1 is used as the input layer to input the data to be processed; Layer(t) is used as the output layer to output the calculation results. Layer2~Layer(t-1) are the hidden layers in the neural network, and the specific calculation and processing process is implemented in these layers.

As shown in the figure above, this is a system diagram of the hybrid digital-analog storage and computing chip to implement neural network operations, in which multiple flash memory processing arrays are grouped to obtain t-2 flash memory processing array groups: the 1st flash memory processing array group to the t-2nd flash memory processing array group are respectively used to implement Layer2 to Layer(t-1) in the above neural network, and the remaining two arrays are used as the input and output layers of the neural network.

When processing a specific model, the digital-analog hybrid storage and computing chip sets the threshold voltage of each programmable semiconductor device according to the weight parameters of the trained neural network, and then inputs the data to be processed into the digital-analog hybrid storage and computing chip for calculation, thereby realizing the forward propagation application process of the neural network.

The above is the digital-analog hybrid storage and computing integrated chip invented by Zhicun Technology for AI computing. This chip can effectively reduce the design complexity and manufacturing cost based on the realization of the digital-analog hybrid storage and computing functions, which is conducive to large-scale industrialization. At the same time, each flash memory processing array can operate independently, and then each flash memory processing array can be selectively used according to different needs to achieve different functions, thereby increasing the flexibility of the design.