RISC-V basic instruction set architecture and privileged architecture specifications approved

On July 10, the RISC-V Foundation announced the approval of the RISC-V base instruction set architecture and privileged architecture specifications, which is a milestone in the development of the RISC-V ecosystem.

The RISC-V base instruction set architecture is used for the interface between software and hardware. Software coded to this specification will continue to work on RISC-V processors forever, even as the architecture evolves through the development of new extensions.

Krste Asanović, Chairman of the Board of the RISC-V Foundation, said that RISC-V uses a simple fixed basic ISA and modular fixed standard extension design, which helps prevent fragmentation while supporting customization. The RISC-V ecosystem has previously demonstrated a great degree of interoperability in various implementations. Now that the basic instruction set architecture has been approved, developers can further rest assured that the software they write for RISC-V will always run on all similar RISC-V cores.

The privileged architecture is used to provide protection between different components of the software stack, and attempts to execute the current privilege mode, operations that are not allowed will cause an exception to be thrown. The RISC-V privileged architecture covers all aspects of the RISC-V system outside the non-privileged ISA, including privileged instructions and additional functions required to run the operating system and connect external devices. Each privilege level has a set of core privileged ISA extensions with optional extensions and variants, including machine ISA, supervisor ISA, and hypervisor ISA.

Andrew Waterman, chairman of the RISC-V Privileged Architecture Task Group, said that the RISC-V privileged architecture is a contract between RISC-V hardware and software (such as Linux and FreeBSD). The approval of these standards is a milestone for RISC-V. Operating system developers and hardware vendors can implement these specifications with confidence without compatibility issues.

In recent years, global attention to the RISC-V architecture has been heating up. Major manufacturers such as IBM, NXP, Western Digital, Nvidia, Qualcomm, Samsung, Google, Huawei, and Tesla have all made relevant arrangements in the RISC-V direction.

After Huawei was included in the "Entity List" of the US Department of Commerce, the open source instruction set architecture RISC-V has received more attention in China, but there are also voices of doubt, after all, RISC-V technology originated from the University of California, Berkeley. However, many industry insiders believe that the instruction set standard is public and will not be affected by export controls, but commercial designs based on the RISC-V standard may be subject to control.