Design of register keyboard for external interrupt of DM642 and CPLD

Abstract: This paper introduces a keyboard extension method using DM642 and CPLD. CPLD manages the chip logic in the keyboard circuit, and the external interrupt of DM642 monitors the status of the keys. The classification of keyboards is briefly explained, the hardware circuit schematic diagram of the system is given, and the program debugging method in CCS software is used. The simulation results show that the design is feasible and achieves the expected effect.
Keywords: keyboard; DM642; CPLD; human-computer interaction

Introduction
The keyboard is an essential input part in the human-computer interaction module. In the current embedded system human-computer interface, a dedicated keyboard processing chip ZLG7290 is usually used to design the keyboard. Since ZLG7290 is a keyboard management device with 64-bit LED display and 64 keys, it will cause some LED displays and keys to be idle and wasteful and occupy more hardware resources, which increases the cost. With the improvement of the cost performance of DM642, it is more and more widely used in image processing systems and digital media systems. As an important means of human-computer interaction, the keyboard is an indispensable input device in the above systems. Usually, independent keyboards and row-column scanning keyboards are mainly used in circuit systems with DM642 as the core. This paper uses CPLD to provide multiple input/output pins in the DM642 circuit system to expand the keyboard. The external interrupt of DM642 monitors the status of the key, and CPLD manages the chip logic in the keyboard circuit. In addition, CPLD (EPM7128AET chip) has a total of 100 input/output pins, which can be freely expanded according to actual needs, which is flexible and has broad application prospects.

1 Independent keyboard and row-column scanning keyboard
1.1 Independent keyboard
Independent keyboard refers to a keyboard that connects each key directly to the I/O input line in a one-to-one manner. Independent keyboards can work in multiple modes: interrupt mode, program query mode, timed query transmission and interrupt query mode. The disadvantage of independent keyboards is that they need to occupy more I/O lines. When the application system requires fewer keys or more I/O lines, a single key can be directly connected to the input/output pin of the DSP, and the key value can be detected by query or interrupt mode. The circuit is shown in Figure 1. S1~Sn represent n keys. The input end of the key is grounded, and the output end is connected to the DSP input/output pins P1~Pn and connected to a pull-up resistor. The DSP can use the query method to detect the key value, or use the interrupt method to monitor the state of the key.

1.2 Row-column scanning keyboard
The row-column scanning keyboard is the most important type of row-column keyboard. It is a keyboard composed of n I/O lines as row lines and m I/O lines as column lines. A key is set at each intersection of the row and column lines. In this way, the number of keys in the keyboard is m×n. It is suitable for keyboards with a large number of keys. This type of keyboard structure can effectively improve the utilization rate of the I/O port in the system. The row-column scanning type first makes the column (row) lines all output low level, and then judges the state of the row (column) lines. If the row lines are all high level, it means that no key is pressed. If the row lines are not all high level, it means that a key is pressed. Then make the column lines low level in turn, and then judge the state of the row lines. When the row lines are all high level, it means that the pressed key is not in this column. When the row lines are not all high level, it means that the pressed key is in this column. The state of the row line and the state of the column line at this time are combined to get the position of the pressed key. The scanning method uses row (column) scanning to obtain the position of the key. When the pressed key is in the last row, it needs to be scanned N times (N is the number of rows). When N is large, the keyboard works slowly. As shown in Figure 2, the keyboard is a 16-key row and column scanning keyboard with 4 input pins Pn~Pi4 and 4 output pins Po1~Po4. When the DSP works in the query mode, the keys do not need to be added with pull-up or pull-down resistors.

2 Register keyboard with external interrupt
2.1 Overall system structure
The CPLD in the keyboard system uses the EPM7128AET chip, which can provide multiple input/output pins, with an output logic level of 3.3 V, and input logic levels compatible with 3.3 V and 5 V, with a total of 100 input/output pins. CPLD has many advantages in logic control and timing control. It has a large number of logic gates inside, which can be cleverly used in the software environment to design various logic combinations of input pin signals and provide the logic combination signals to the output pins. The CPLD device also provides a large number of standard logic circuit modules, such as decoding circuits, address latch circuits, etc. These circuit modules replace the decoding chips and address latch chips required in traditional circuits, which not only saves space for circuit board design, but also makes the circuit design process more flexible and convenient. The DSP uses the TMS320DM642 chip. In order to expand the GPIO input/output pins of the DM642 and design a 16-key keyboard, the CPLD needs to use the lower 8-bit data bus D[7:0], address bus EA[10:3], EA22 and read/write control signal lines of the DM642 so that the CPLD can generate the required extended registers internally. The CPLD has abundant input/output pins and a large number of logic gates to manage the chip logic in the keyboard system. As shown in Figure 3, the 16 input terminals of the key are grounded, the output terminal KEY[1:16] is connected to the input pin I[1:16] of the CPLD chip, the output terminal is connected to a pull-up resistor, the lower 8-bit data bus D[7:0], address bus EA[10:3] and EA22 of DM642 are connected to the input/output pin I/O[1:18] of the CPLD device, the RE and WE signals of DM642 are read/write enable signals for register expansion, the space chip select signal CE1 and the address signal EA22 are used as register port chip select signals, and the key status read port is mapped to the CE1 space of DM642. When a key is pressed, a rising edge pulse trigger signal is generated, which can be considered as an external interrupt event, so the interrupt event can be responded to through the external interrupt EXINT4 of DM642, and EXINT4 can be mapped to interrupt INT4 inside DM642. DM642 reads the key value of the key through the data address bus in the interrupt function corresponding to INT4 and analyzes it. At the program level, the trigger signal of the button corresponds to the interrupt service function of INT4 in the program, and the interrupt service function of INT4 is linked to the interrupt number in the interrupt vector table.

The logic diagram of the 16-bit input port control register of the extended key state inside the CPLD chip is shown in Figure 4. DM642 reads the key value of the key and analyzes it by operating the register read port. In Figure 4, the space chip select signal CE1 and the address signal EA22 of DM642 are used as the register port chip select signals. When the CE1 signal is low-level valid, the register address related to the keyboard state is mapped to the CE1 space, and the address line EA22 is low-level valid in the mapping relationship. The effective range of the CE1 space address is 0x90000000~0x9FFFFFFF, the register port address of the keys KEY1~KEY8 is 0x90080019, and the register port address of KEY9~KEY16 is 0x9008001A. KEYCS[2:1] is the chip select signal line of the input port, and the two input chip select signals correspond to the I[1:8] and I[9:16] input pins respectively. Chip 74138 is a decoder provided inside the CPLD, and chip 74373 is an address latch provided inside the CPLD, which is used to latch the level state when a key is pressed.

Here, the extended register port address is set to PORTAdd. PORTAdd has a 32-bit port address in the CE1 space. The definition relationship between PortAdd[31:0] and the CE1 signal and EA[22:3] address signal of DM642 is listed in Table 1. The CE1 signal determines the PORTAdd31 bit, and the EA[22:3] address signal determines the PORTAdd[19:0] bit of the register port address. The other bits of the PORTAdd port are reserved. According to the mapping relationship in Table 1, the physical address of the internal register port of the CPLD can be determined. In Figure 4, the 74138_1 chip is selected when the CE1 signal remains at a low level and the EA22 signal remains at a high level, then the 31st and 19th bits of PORTAdd should both be high level "1"; EA8~EA6 are high-order decoding address lines, EA5~EA3 are low-order decoding address lines, and the two 74138 chips can be used together to generate 64 chip select signals; the chip select signals KEYCS1 and KEYCS2 are valid at a low level, and the addresses of the two 74373 chips in the CE1 space of DM642 are 0x90080019 and 0x9008001A respectively.

3 Software Design
In the CCS programming environment, write files such as main. C, boot. asm, ves_dm642. asm, and key. cmd. Since CSL contains the boot. asm function, you only need to write main. c, ves_dm642. asm, and key. cmd files by yourself, and then add them to the created Key. pjt project.
ves dm642. asm is the interrupt vector table file of DM642, which declares the interrupt function name and the mapping relationship with the interrupt number. KeyIsr is the key interrupt response function corresponding to INT4. Its main code is as follows:

main. c is the main program of the keyboard circuit, including adding the header file of the CSL library file, defining the port address of the key status register and the key MASK, initializing the EMIFA interface, and the key analysis function. The main code is as follows:



4 System Debugging
In order to debug the program, you need to add the main. c, boot. asm, ves_dm642. asm, and key. cmd files to the project Key. pjt. At the same time, you need to set the Compiler and Linker property pages in Build Options, and finally compile, link, and download. Set breakpoints and probes to perform software simulation debugging. CCS simulation shows that the program can read the key values ​​and analyze the key status according to the requirements of hardware design, achieving the expected results.

Conclusion
The method of combining DM642 and CPLD to expand the keyboard, the external interrupt of DM642 monitors the status of the key, and the CPLD manages the chip logic in the keyboard circuit. Make full use of the advantages of DM642's GPIO port pins that can be configured as general input/output pins and the rich input/output pin characteristics of CPLD. It can be applied in the human-computer interaction module of the pattern recognition and image processing system with DM642 as the core processor, and has broad prospects.