Design of deadbeat control inverter using DSP

In the early 1960s, Kalman, a famous American control theory expert, proposed the idea of ​​deadbeat control for digital control. With the development of power electronics technology, deadbeat control was applied to inverter control in the mid-1980s. It has the characteristics of fast instantaneous response, high precision, and low THD, and is an excellent control strategy.

At present, technologies such as instantaneous PID control and repetitive control play an important role in applications. However, both technologies have shortcomings that are difficult to overcome, such as the difficulty of digitizing instantaneous PID control and the slow dynamic response of repetitive control.

As computers and various precision automation equipment and electronic equipment are widely used in communications, industrial automation control, office automation and other fields, inverters, as an important part of UPS, have developed rapidly in recent years. The control of inverters has become a research focus, which requires high steady-state accuracy of output waveform, low total harmonic distortion and fast dynamic response. 1 Control principle of deadbeat control inverter

Deadbeat control is a fully digital control method that uses the high-speed numerical calculation function of the microprocessor through digital instantaneous feedback of the state. Figure 1 shows the main circuit of the inverter, which consists of an inverter bridge, an LC filter and a resistive load. LCR can be expressed by the state equation:

In the inverter system, Uin is the output of the inverter bridge and is an intermediate variable; only the pulse width ΔT is the original control variable. In addition, the inverter main circuit can be considered as a mixed analog-digital circuit, so it is more convenient to analyze using discrete variable state equations. For the circuit shown in Figure 1, Uin can be unipolar or bipolar. If Uin is bipolar as shown in Figure 2, then equation (1) can be discretized ^{[1] [2]:}

Equations (2.a) and (2.b) correspond to (a) and (b) of Figure 2, respectively. Take the first row of the matrix equations (2.a) and (2.b), respectively, and let U?C(K+1)=U?*?C(K+1), where U?*?C is the reference sine, and the required pulse width can be calculated accordingly. Then, at the beginning of each switching cycle, U?C and I?C must be detected first (the bus voltage E changes slightly, so it is not necessary to detect it accurately on time), and then ΔT is calculated. Therefore, in actual systems, three sensors and A/D converters are usually required to detect the DC bus voltage, output voltage, and filter capacitor current. Since both A/D conversion and calculation require a certain amount of time, the maximum value of ΔT is limited. As can be seen from Figure 2, if the output is positive, Figure 2a is used, then ΔT≤0.5T. Therefore, there is enough (T-ΔT)/2 time for sampling and calculation.

The output phase of a common PWM inverter is quite different when it is unloaded and fully loaded. This is because the output phase of the inverter bridge is in phase with the given sine wave, but the phase shift of the LC filter is related to the load. The output phase of the deadbeat control inverter remains basically unchanged. It compensates for the phase delay of the LC filter by adjusting the output phase of the inverter bridge.

2 Implementation of deadbeat control inverter

The third-generation digital signal processor (TSP) TMS320F240 series developed by Texas Instruments has 16-bit high-speed fixed-point computing capabilities. This type of digital signal processor chip has the following advantages:

(1) Very high processing speed. The single instruction execution cycle is 50ns, which means that 20 million instructions can be executed per second. The chip has a dedicated 16*16 hardware multiplier, an 8-level hardware stack and a four-level pipeline processing structure, which greatly improves the processing speed of digital signals. The 544kB high-speed on-chip bidirectional access RAM enables high-speed transmission of on-chip data;

(2) Unique parallel structure. In the traditional von Neumann structure, the program code and data units are uniformly addressed, while the F240 uses an improved Harvard structure, where the program area and data area storage units are separated, and instruction fetching and data access can be performed simultaneously. This further improves the processing speed;

(3) The rich instruction set provides flexible programming capabilities. It can not only realize various arithmetic and logical operations, but also easily complete the information transfer between the program area and the data area;

(4) Highly integrated internal resources. A dedicated event manager is embedded in the chip, which can easily capture event interrupts and output various PWM waveforms. The chip also integrates peripheral functions such as A/D converters, serial communications, and I/O interfaces, making it very easy to construct a control system and greatly reducing hardware overhead.

Due to the above advantages, the DSP F240 series is particularly suitable for the real-time and high-speed processing required for digital control. Its internal resources include:

(1) Three independent 16-bit hardware timers with six operating modes; output a total of 12 PWM pulses, which facilitate the control of power electronic converters such as single-phase half-bridge, full-bridge and three-phase full-bridge (with configurable dead zone and space vector PWM control);

(2) It has three external hardware interrupts and four external event capture interrupts (Capture). The system has software resources such as RESET interrupt, power-off interrupt PDPINT, and non-maskable interrupt NMI, which provide guarantees for the safety of the system and can handle special events in a timely manner.

(3) Two independent 10-bit precision A/D sampling converters, an internal clock unit with a PLL phase-locked loop, a watchdog monitoring unit, a serial synchronous port SPI and a serial asynchronous port SCI, 28 programmable multiplexed I/O ports, etc.

From the above internal resources, it can be seen that the TMS320F240 series DSP does not require too much hardware overhead when designing a control system, thereby improving the reliability of the system.

3 Simulation and Experimental Results

Under ideal conditions, MATLAB is used to simulate the deadbeat control half-bridge inverter. Its circuit parameters are: L=1mH, C=20μF , switching frequency is 10kHz. DC bus voltage E=300V, output 50Hz, 100V peak AC. Its output waveform is shown in Figure 5.

The experiment makes full use of the event manager function and interrupt of TMS320F240 to achieve deadbeat control. Figures 3 and 7 are flow charts of the control main program and interrupt service subroutine. The main program includes initialization (opening and setting corresponding interrupts), start detection and soft start; the T1 cycle interrupt service program includes reading the sine table, coefficient calculation and starting bus voltage detection, as shown in Figure 4. The T2 underflow interrupt service program is used to start the detection of U _C and I _C. The A/D completion interrupt service is used to handle the data storage after the bus voltage detection is completed and the calculation of ΔT after the U _C and I _C detection is completed, as shown in Figure 6. Figure 8 is the timing distribution diagram of the interrupt service program , 1 and 3 are the T1 cycle interrupt service program and the T2 underflow interrupt service program respectively; 2 and 4 are the two responses of the A/D completion interrupt service program. Among them, 1 and 3 differ by 50μs (0.5T), and 1, 2 and 3, 4 differ by 7μs (the time required for A/D conversion). Figures 9 and 10 show the output waveform of the inverter and the proportion of each harmonic. According to Figure 10, the harmonic distortion rate can be calculated to be 0.8%.