Use SPI interface to realize dual DSP bidirectional communication and synchronization

Abstract: In order to realize the bidirectional data communication and synchronization between two TMS320F2812 DSPs, the hardware circuit design and software protocol implementation scheme of using the serial SPI peripheral interface module integrated inside the TMS320F2812 DSP to realize the bidirectional data communication and task synchronization of dual DSP controllers are given. The experimental verification shows that the scheme can meet the high-efficiency and high-reliability bidirectional data communication and task synchronization between the two DSPs. Finally, a solution to the faults in the communication process is proposed. The problem of bidirectional data communication and task synchronization of two DSP controllers is successfully solved.
Keywords: DSP; SPI; bidirectional communication; synchronization

In the actuation systems of cutting-edge technology fields such as manned spaceflight, unmanned aerial vehicles, and fire control radar, dual controller redundancy technology is often used to improve system reliability. An efficient and reliable data communication is required between the two controllers to ensure that the same periodic tasks are executed at the same time. The SPI interface can be used to achieve bidirectional data communication. The TMS320F2812 DSP chip has an SPI module integrated inside. The scheme proposes a bidirectional communication and task synchronization between two DSPs based on the SPI communication interface. One of the two DSPs is fixed as the SPI communication master and the other as the SPI communication slave [1]. Finally, a solution to communication failure is proposed.
1 DSP SPI peripheral interface module and SPI communication principle
1.1 SPI peripheral interface module
The TMS320F2812 DSP chip has an SPI module integrated inside. Its data transmission rate and character length are programmable. The maximum transmission rate can reach 10 Mb/s and it supports master/slave mode communication [2]. The interface between the SPI peripheral module and the DSP CPU is shown in Figure 1. It includes four external pins, uses the low-speed peripheral clock LSPCLK as the clock source, has two independent peripheral interrupt request signals (SPIINT/RXINT and TXINT), and provides 12 registers to implement the configuration and control of the SPI module.

There are four main external pins for communication between SPI devices:
SPISOMI: For the master device, this pin is data input; for the slave device, this pin is data output;
SPISIMO: For the master device, this pin is data output; for the slave device, this pin is data input;
SPISTE: The enable pin sent by the master device to the slave device;
SPICLK: The serial clock pin of the SPI interface, the master device provides the synchronous clock to the slave device.
1.2 SPI communication principle
The SPI interface can be configured in two modes, namely master control mode and slave control mode. Figure 2 shows the connection relationship between two controllers (master controller and slave controller) using the SPI interface. The master controller starts data transmission by sending the SPICLK signal, and the master and slave controllers can send and receive data at the same time.

In master controller mode, SPI provides the clock for the entire serial communication network through the SPICLK pin. At this time, the serial data to be sent is shifted out from the pin SPISIMO, and the data is received on the pin SPISOMI. In system applications, the pin SPISTE of the master controller is used to control the chip select signal of the slave controller. When data is communicated between the master device and the slave device, the master device sets SPISTE to a low level to enable the slave device. At this time, the serial data of the slave device is shifted out from the SPISOMI pin and shifted in from the SPISIMO pin. When the data transmission is completed, the SPISTE pin is set to a high level.
Write data to SPIDAT or SPITXBUF, start the SPISIMO pin to send data, first send the most significant bit MSB of the SPIDAT register, and the received data is shifted into the least significant bit LSB of SPIDAT through the SPISOMI pin. After the specific data bit is transmitted, the received data is stored in the SPIRXBUF register to be read and used. When the data length is set to less than 16 bits, the received data stored in the SPIRXBUF register is right-aligned, while the transmitted data needs to be written into the SPIDAT or SPITXBUF register in a left-aligned format [3]. Figure 3 shows the SPI data transmission format.

2 System hardware interface design
The system uses TI's TMS320F2812 DSP chip as the controller, and uses the SPI interface to realize controller data communication and task synchronization, that is, the same system executes the same task at the same time. It integrates an SPI peripheral module internally. To realize SPI data transmission, you only need to configure a few corresponding registers.
SPI transmission can only be initiated by the master controller, and the master controller provides clock and enable signals for the slave controller. This design uses the DSP's internal integrated peripheral module. When the master controller sends data, it enables the slave controller through SPISTE, and then starts SPI transmission. If the slave controller needs to actively send data to the master controller during the communication process, the master controller can only send pseudo data to provide the slave controller with clock and enable signals.
3 System software design
3.1 Synchronous design implemented by software
The main idea of ​​​​realizing task synchronization is the response mode in network communication. The specific flow chart is shown in Figure 4. During the communication process, SPI may be interfered by external factors, resulting in data transmission errors. The synchronization process is a dead-waiting process. The use of SPI software reset can solve this problem. If it is found that the correct ACK signal cannot be received during the communication process, the software reset is performed and the transmission is restarted. This method has been verified in practice and the effect is very good.

3.2 Software Communication Protocol Design
There are two situations for SPI-based communication: communication initiated by the SPI master and communication initiated by the SPI slave. In this scheme, active data transmission and interrupt data reception are adopted. By configuring the SPI register, setting the data length and communication rate, enabling enhanced FIFO transmission and reception, and using 7-level interrupts to receive data, that is, an interrupt is triggered after receiving 7 data, and the data in SPIRXBUF can be read from the interrupt. Since SPI itself does not specify the start and end of data, in the actual communication process, an interface communication protocol needs to be made for the communication between the master controller and the slave controller [4].
In the design, data is sent in a packet manner. A packet header is sent in front, which contains parity (1 bit), data type (8 bits) and packet length (data length 4 bits). The actual application data is sent after the packet. The length and type of the actual data can be determined based on the packet header. Figure 5 shows the data frame structure of the packet.

In this case, the transmission process of an SPI can be described as follows: the master controller first sends a packet header to inform the slave controller of the type of data being transmitted and the length of the data. After the 7 data are transmitted, an interrupt reception is performed, and the parity bit of the first word is first judged. If it is wrong, the software is reset, and the data is received and judged again; if it is correct, the data length and data type are checked, and read into a specific variable according to the specified data length and data type. If the data type received this time does not correspond to the specified data type, it is also considered that the data transmission is wrong, and the software is reset, and the data is received and judged again. Both the master and the slave use interrupts to receive data. The master controller takes the initiative to send, while the slave controller reads the data first and then sends specific data in the interrupt service subroutine after the interrupt is generated. The reception mode judgment of the master and the slave is exactly the same. During the communication process, sometimes the slave controller needs to actively send a set of data, and the master controller needs to provide the slave controller with a clock and an enable signal before the slave controller can send data. Using the master controller to send pseudo data can solve this problem. In the software protocol, it is stipulated that the first word (packet header) of SPI is all zero (0X0000) as pseudo data. When the packet header receives pseudo data, it does not judge the parity check, data length and data type, and directly discards it.
3.3 Communication fault handling solution
In the actual application system, the communication environment of SPI is complex, which may affect the transmission of SPI. Since SPI is a serial data transmission, once a fault occurs, it will affect the subsequent data transmission if it is not eliminated. Therefore, this problem must be solved. In this solution, it can be found out whether the SPI communication has a fault based on the judgment of the parity check and data type. If a fault is found, the fault must be eliminated and isolated to avoid affecting the subsequent data transmission.
The software can eliminate and isolate the fault. The software reset function of SPI can be used to reset and enable after judging the error. It can be set by setting the SPIRST bit in the SPI FIFO transmit buffer register SPIFFTX. When writing 0, the SPI transmit and receive channels are reset, but the configuration of the FIFO register remains unchanged. When writing 1, the SPI FIFO restores the transmit and receive channels without affecting the SPI register configuration.
4 Experimental results
In this scheme, the main frequency of DSP is 120 MHz, the low-speed clock of SPI is 30 MHz, and the data transmission rate is configured to 7.5 Mb/s. The test results show that SPI can well meet the high-speed communication between two DSPs. In the actual test application, it is found that under normal circumstances, SPI communication is normal and no communication errors occur; but under certain external interference, communication errors will occur. For example, in the actual DSP application system, DSP is used to control the motor. When the motor is commutated or the speed is relatively high, it will affect the SPI transmission and data transmission errors will occur. At this time, software reset is required. The communication rate of 7.5 Mb/s is selected after multiple comparisons. If the rate is low, the probability of error is high and the system is unstable; if the rate is too fast, it will affect data transmission and data loss.
The SPI interface is simple to implement, occupies less I/O resources, and has a fast transmission speed [5-6]. It solves the problems of SPI bidirectional data transmission, task synchronization and SPI communication failure in the actual application system from the aspects of software and hardware, successfully realizes bidirectional communication between two DSPs, and uses software instead of hardware to realize task synchronization. It also proposes a solution to SPI communication failure. It can be used for high-speed data transmission and synchronization between multiple controllers.