Implementation of high-speed line scan camera based on DSP

　　Modern production and scientific research have increasing demands on image acquisition systems. As a front-end device for digital image acquisition and transmission, high-speed line scan cameras’ scanning speed and quality largely determine the performance of the entire system. Line scan cameras on the market are very expensive, so there is a need to develop affordable high-speed line scan cameras.

　　Designing a high-speed line scan camera includes the hardware structure of the camera itself and the related software for camera operation. From the perspective of the camera structure, the line scan camera is an image acquisition and visual information acquisition device, and its main function is to convert optical image signals into digital image signals. Generally speaking, it consists of an optical imaging part, a photoelectric conversion part (converting analog optical signals into analog electrical signals), and A/D conversion. The photoelectric conversion part is generally implemented by a solid-state image sensor.

　　　Figure 1 System structure diagram of camera

Figure 2 Functional block diagram of the clock signal and control signal generated by the camera's internal CPLD

Figure 3 DSP camera workflow diagram

Introduction to TMS320C6201
　　TMS320C6201 is mainly composed of three parts: CPU, peripheral devices and memory. The address bus of C6201 is 32 bits, so the addressing range reaches 4GB. Its memory space can be divided into four parts: the on-chip program space can be used as Cache, on-chip data space, external storage space and internal peripheral device space. The address range of each space can be flexibly set by setting the five BOOTMODEs. The on-chip data RAM includes four 8K×16bit blocks. These blocks are interleaved, allowing the CPU to access two different blocks of the data RAM at the same time without conflict, improving the ability to read and write data in parallel. For larger programs, the on-chip program RAM can be used as a Cache to store frequently used codes, reducing the number of off-chip accesses and thereby increasing program running speed. Different from common chips, C6201 has eight functional units, divided into two groups. Each group includes a multiplier Mn and three arithmetic and logic operation units Dn, Sn, and Ln. They perform multiplication operations, addition and subtraction operations, linear and circular address calculations, and arithmetic and logical operations respectively. Because the input/output ports are independent of each other, the eight computing units can achieve parallel processing. Each group of computing units corresponds to a data path and can be used for circular address calculation.

Design and implementation of line scan camera
　　The system structure of this line scan camera is shown in Figure 1.

CCD analog image data acquisition part
　　This part includes CCD sensor and CCD signal processing channel chip. It mainly consists of image sensor IL-P1-4096 and CCD signal processing channel chip VSP2254. Its main function is to convert simulated light distribution information into digital image data. This part of the circuit receives various working clocks and various acquisition control signals provided by the CPLD, and outputs corresponding digital image data.

DSP data processing part
　　This part includes the buffer chip of digital image data, the processing chip and the processed data temporary storage chip. The main function of this part is to process the digital image data sent from the image acquisition part, and store the processed data into the corresponding storage unit. This part is composed of DSP chip TMS320C6201, FIFO data buffer circuit, dual-port RAM and other chips. In this circuit, the FIFO data buffer circuit not only receives the write clock and write control signal from the CPLD, but also receives the read clock and read control signal from the DSP chip. The input of the FIFO data buffer circuit is connected to the CCD channel processing chip VSP2254, and its output is sent to the 32-bit internal data bus under the control of the DSP. DSP provides different control signals to CPLD according to different working modes. These signals are processed by corresponding logic inside the CPLD and then serve as control signals for other parts. The DSP chip also provides corresponding read and write control signals for the dual-port RAM and corresponding DMA services for its data transmission. On the one hand, the dual-port RAM receives the processed image data from the DSP, and on the other hand, it provides preparation for data transmission. Dual-port RAM works under the dual control of DSP chip and CPLD logic circuit.

Clock and control signal generation circuit
　　This part includes the CPLD clock generation logic circuit and control logic circuit. The circuit is mainly composed of CPLD chip LC4128V100 and its peripheral circuits. The clock circuit of the camera mainly implements two functions: 1. Provides the basic clock required for camera operation, which includes the clock required for the operation of the CCD sensor and the working clock provided for the CCD signal processing channel (i.e., the CCD signal front shoulder sampling clock SHP, CCD signal sampling clock SHD, CCD signal dummy shielding clock CLPOB, CCD signal black level bit clock CLPDM and data transfer clock ADCCK), output synchronization clock DIR-STROBE and output row valid provided for the output circuit Synchronous clock DIR-LVAL and provides a 50MHz working FSB for the C6201 (this clock is output to 200MHz after being multiplied by 4 inside the C6201 as the DSP main frequency). 2. Together with the control signal output by the DSP, it forms a combinational logic circuit to realize the control of the peripheral circuit by the DSP chip (including the control of the flash memory chip AT49LV409, the dual-port RAM chip IDT70V261S, the FIFO chip IDT723635, as well as the external interface circuit and CCD signal acquisition circuit) . Judging from the functions of the above clock and control signal generation circuits, the programmable logic chips used to implement their functions must meet certain performance requirements. From the perspective of delay, since the internal access reference clock is 200MHz, the delay between chip pins is required to be less than 5ns, and the timing is better controllable. From a capacity perspective, there must be enough macro cells to achieve the above functions. The control function block diagram is shown in Figure 2.

Power supply and data output circuit
　　This part includes the CPLD address generation circuit and the LVDS data upload circuit. Its function is to provide the power required for the camera to work and complete the communication with the PC (this includes uploading the processed image data to the PC, receiving PC control signals, etc.). The power circuit provides several sets of power supplies such as +5V, -5V, +1.8V, +3.3V, and +15V for the entire camera. Among them, +5V is the main power supply for the whole machine.

　　The amount of image data collected based on horizontal scan line technology is relatively large. To upload images with large amounts of data to the computer in real time and quickly, there are certain requirements for the transmission rate of the data transmission interface. Among the several current computer interfaces, the one that can meet fast communication requirements and is easy to use in design is the LVDS interface. Moreover, the interface has strong driving capability and can transmit data at high speed in both directions. Chips DS90C31B and DS90C32B are data transceiver pairing chips specially used for LVDS interfaces. DS90C31B is a data sending chip, and DS90C32B is a data receiving chip. The control of these two chips is very simple, and the data transfer rate can reach 155.5Mbps (77.7MHz). However, in order to suppress signal reflection and balance differential signals during circuit connection, a 100 Ω resistor must be connected to each set of signal loops.

The working mode and process
　　of line scan camera comprehensively consider the working mode of the camera to adapt to different working environment requirements. Its working mode is divided into four categories: active real-time acquisition, active non-real-time acquisition, passive real-time acquisition, and passive non-real-time acquisition. kind. Due to space limitations, each working mode is not described in detail here. The workflow of the line scan camera is shown in Figure 3.

Conclusion:
　　The high-speed digital camera design proposed in this article is generally feasible and can realize the collection of dynamic images.