A PLL-based test and measurement clock recovery solution

Whether placed in a test setup or as part of a device under test, clock recovery plays an important role in making accurate test measurements. Since most gigabit communication systems are synchronous, the data within the system is timed with a common clock. Whether traveling along a few inches of circuit board or across a continent via fiber, the relationship between the data and the clock it is timing into can become disrupted. By extracting the clock directly from the data, the signal can be properly regenerated at the receiver.

It is important to note that a receiver typically improves the incoming data signal before it is transmitted onward. The decision circuitry in the receiver retimes the data to square the waveform. This process relies on a clock signal that is synchronized with the incoming data. Clock recovery within the receiver achieves this goal, provided that the retimed clock moves in the same manner and at the same time.

PLL-Based Clock Recovery

Clock recovery can be achieved through different architectures, the most common being a phase-locked loop (PLL) based approach in measurement equipment. A recovery circuit is used to derive a clock that is synchronized with the incoming data, based on the transitions seen in the data. The PLL must remain locked for data segments that have multiple strings of identical bits. The loop gain has the most significant effect on the loop bandwidth, and any filtering within the loop filter will generally have secondary effects. It should be noted that the transition density of the input data affects the energy entering the loop, which in turn affects the characteristics of the loop. Therefore, the loop bandwidth in a compliance test will vary depending on the transition density of the chosen pattern.

The system transfer function performs a low-pass filtering operation on the phase modulation of the input signal, while the error response transfer function performs a high-pass filtering function. The loop tracks the input phase modulation within the loop bandwidth while failing to track the phase modulation outside the bandwidth. This allows the loop to track low-frequency jitter while ignoring high-frequency jitter outside the PLL loop bandwidth.

One measure of a PLL's jitter tracking characteristics is the loop bandwidth (LBW), which is usually measured at the point where the "jitter in/jitter out" transfer function is -3dB. But this is not the only way to characterize a loop.

A wide LBW improves jitter tolerance, while a narrow LWB removes more jitter from the recovered clock, which is beneficial to downstream synchronizers but reduces jitter tolerance. Although a wide LBW seems to be the ideal choice, cost and technology are usually considered. A wide LBW also introduces more noise or random jitter. The LBW used in current measurements is generally in the range of 1 to 10 MHz.

Clock recovery input and output

It is important to point out how clock recovery is used in the measurement and where errors can occur. For example, on the transmitter test side, there are usually two main reasons why clock recovery is required: no clock signal is provided as a trigger for the test equipment, or the standard requires the use of a specific LBW for jitter measurements (see part a in Figure 1). In the latter case, the purpose is to use the system receiver (such as the BERTScope BSA Series) to include clock recovery to track part of the input jitter, so that the transmitter test should only involve high-frequency jitter that is not tracked by the receiver (see Figure 1).

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It can be seen that for signals under test with jitter components close to the clock recovery LBW, incorrect LBW settings can result in inaccurate jitter measurements. Sometimes the standard will hint at the use of clock recovery in the test, such as mentioning a "golden PLL" or specifying that jitter is to be measured "after applying a single-pole, high-pass, frequency-weighting function that attenuates jitter at 20 dB/decade to below the frequency of (bit rate/1,667)."

Spread spectrum clocking (SSC) spreads the clock energy (and data) over a 0.5% frequency band, reducing the average power at a given frequency in the spectrum. This can help products meet regulatory requirements for radiated and conducted emissions. To successfully track SSC, the receiver must be able to track the modulation (including its harmonics) to avoid eye closure. If the loop response does not adequately track SSC, or if incorrect delays are introduced between the clock and data paths, the test eye will be ambiguously closed.

Incorrect peaking (i.e., the area near the LBW where the jitter output of the clock recovery equipment may be greater than the jitter input) can inflate the amount of jitter being measured. Additionally, trigger delays in the test equipment relative to the input data signal can cause incorrect jitter measurements. For example, a fixed delay in the measurement system can cause additional apparent jitter to be measured. The amount of added jitter depends on the jitter frequency relative to the amount of delay.

On the receiver side, clock recovery may occur in the DUT or as part of the test equipment calibration procedure. Clock recovery is frequently found in the DUT and is often implemented in the test using stress and sinusoidal jitter (see part b in Figure 1). In the case of sinusoidal jitter, the test typically uses a mask that applies more jitter at lower modulation frequencies or less jitter at higher frequencies.

Problems include using an improperly designed LBW in the receiver, which can cause the jitter tolerance mask to fail. Incorrect slope of the tracking response can cause insufficient accuracy in tracking the SSC, resulting in smeared closure of the test eye and bit errors.

Clock recovery is frequently used in test equipment setup and calibration of receiver jitter tolerance or stressed eye signals (see part c in Figure 1). Sinusoidal jitter is often set to a frequency higher than the LBW of the clock recovery during calibration. However, an incorrect LBW may result in the wrong amount of stress being set, which can result in understressing or overstressing the device under test, increasing the likelihood of customer rejection and affecting yield.

From all of these, it is easy to conclude that the LBW setting is critical and has a significant impact on the jitter observed in the measurement. Changing the loop bandwidth can reveal the jitter spectrum. Testing with a very narrow LBW will reveal all the jitter generated by the transmitter under test. Testing with a very wide LBW will only reveal the jitter generated by the transmitter that the intended system receiver cannot filter out with its own PLL. Generally, the latter clock recovery method is specified in compliance testing. System designers are mainly concerned with jitter that is beyond the tracking capability of the receiver.

Distributed clock solution

Not all systems derive timing from the data stream. Some systems, such as PCI Express and fully buffered dual in-line memory modules (DIMMs), use distributed clocks sent to each end of the communication link to time the data. The transmitter and receiver use PLLs to generate the reference clock.

Generally speaking, a distributed reference clock will have some amount of jitter, such as phase noise from the original crystal. It may also have SSC. The clock is regenerated within each IC and used to clock both the transmit and receive functions. Each PLL will have a loop response, and if they act exactly the same, then jitter on one PLL can be tracked exactly by the other, i.e., the receiver sees no net effect. But the reality is often more complicated.

It is almost impossible to obtain identical loop responses even for devices made with the same design, same manufacturing process, and same production batch. Since it is also difficult to ensure the same path lengths between ICs and within ICs, equivalent trigger delays will also appear in the receiver jitter, resulting in more jitter. [page]

Embedded Clock Solution

Embedding the clock into the data is a common way to ensure that the transmitted data stream is accurately recovered at the receiver. However, once this is done, a problem arises: the system is running at one clock rate, while the incoming bit stream runs at a slightly different rate. The data input must be re-clocked in some way to match the receiving system.

In some architectures, particularly SONET/SDH, an important job for designers is to make all the clocks in the system match as closely as possible. This is achieved by distributing highly accurate system clocks based on the Global Positioning System (GPS) or by distributing local clocks based on Rubidium or similar standards.

Other architectures tolerate greater differences in clock rates to reduce cost and complexity. In any case, the system must eventually handle any mismatches, typically by waiting until the difference exceeds 1 bit or 1 frame, and then inserting or deleting bits or characters. Often, the system protocol inserts multiple characters, called fill words, which are discarded at the receiver. Other times, the protocol allows the receiver to insert its own characters if necessary without disrupting the meaning of the data.

Adding or removing these characters can significantly impact testing. Protocol-based test equipment is often set up to handle inserted or removed characters while still being able to recognize the underlying information. However, physical layer test equipment is sometimes more limited and requires the pattern to exactly match a known repeating sequence with no variations. Extra or missing characters can cause the equipment to think an error has occurred.

Data pattern changes can also occur when the system manages baseline wander, that is, the system goes through AC coupling and a long string of identical bits, causing the average signal voltage to drift until a bit error occurs. In this case, the protocol scheme usually has two versions of each valid character and determines which version is sent to best combat any baseline wander or run inconsistency. The protocol intelligence on the receiver is fully capable of identifying which version is correct, but this also violates the requirement of some test equipment for the pattern to remain unchanged.

Some test equipment can make parametric measurements without repeating the pattern. This is very effective in checking for physical layer problems, but does not handle protocol errors. There is also the possibility of missing receiver errors that are cleared and then retransmitted as correct codes, even though they are problematic.

By using loopback testing, the signal sent to the receiver is looped back and becomes the output of the transmitter. However, the data is not always exactly the same, as errors in clock rate matching can cause fill words to vary, which can confuse the test equipment. In these cases, one solution is to create a test environment where the transmitter clock domain and the receiver clock domain are exactly the same, eliminating the need for domain rate matching. Many schemes using instrument clock recovery can create a clock signal at the exact rate of the test equipment output, and then use this signal to generate a test signal for loopback testing.

As clock recovery becomes more prevalent in more systems and test setups, its impact on measurements must be considered. Many external influences can disrupt the relationship between data and clock sources. By understanding the relationship between the two, more useful and accurate measurements can be obtained.