Research on DSP-based vehicle video processing system

　　Introduction
　　At present, most traffic monitoring application systems are mainly focused on emergency alarm, vehicle positioning and voice communication, and there are not many image applications. Based on this consideration, this paper designs a vehicle image acquisition and processing system. The system collects image information from the rear of the vehicle and transmits it to the front display screen in real time. The driver can observe the rear road surface and vehicle conditions in real time through the display screen. When reversing, he can promptly detect rear obstacles and pedestrians and avoid them safely.

Figure 1 Block diagram of real-time image acquisition and processing system

(a) Timing diagram of collecting a line of images (720 sampling points)

(b) Timing diagram of collecting one frame of image
Figure 2 Digital video signal output timing diagram

Figure 3 The composition and working principle of a real-time image acquisition and processing system
using CPLD to complete video acquisition control 　　. This system collects video data from an analog camera and converts the analog video signal into a digital video signal through a video decoding chip. CPLD serves as a sampling controller to complete the storage and timing control of digital video data. This design uses TMS320C6416 to realize system control and data processing. The specific composition is shown in Figure 1.

Video acquisition module
　　The input of images is completed by an analog camera (this system uses a black and white camera). The camera output is a standard composite video signal (CVBS), which must undergo video decoding and A/D conversion before entering the digital system to be effective. Because analog video signals are very complex, in addition to image signals, they also include horizontal synchronization signals, horizontal blanking signals, field synchronization signals, vertical blanking signals, etc. Therefore, the circuit for A/D conversion of video signals is very complicated. This design uses TI's video decoding chip TVP5146 to complete the conversion from analog to digital video. TVP5146 allows 10 channels of analog video input and has 4 channels of 10bit 30MSPS A/D converters; the field synchronization signal VS, the horizontal synchronization signal HS, the odd and even field signal FID, the clock output signal DATACLK, etc. are all directly derived from the pins, eliminating the need for synchronization clocks Circuit design.

DSP-based image processing module
　　The difficulty in designing a real-time image processing system is how to complete the processing of a large amount of image data within a limited time. Real-time effects can only be achieved when the processing speed of the image processing system reaches more than 25 frames per second. Therefore, in the system design, the processor is the key. The processor is required to have fast computing speed, strong real-time processing capabilities, and also have high-speed memory and I/O access capabilities. This design uses TMS3206416DSK as the video signal processing system. TMS3206416DSK is a low-cost development platform. Users can expand hardware design according to functional needs, which facilitates hardware development and shortens design time.

The CPLD control module
　　TMS320C6416DSK contains a CPLD on the board, which mainly implements the logic control and memory address decoding functions of the system. This design still requires a CPLD to complete the timing control of video storage and display. Altera's EPM7064ATC100 is selected to complete the above functions. Its operating voltage is 3.3V, has 64 logic units, and 68 available I/O pins. The delay time is 4.5ns, and its highest clock frequency is 222.2MHz. The device is based on the EEPROM structure, and the internal structural logic can be edited on-site through the JTAG interface. The programming language is VHDL. The digital video signal output timing is shown in Figure 2.

　　The digital video signal is output according to the timing shown in Figure 2. Taking the NTSC system as an example, Y[9:0] in the figure is the output brightness video signal, DATACLK is the output clock of the line lock system, which is twice the pixel clock frequency, that is, 27MHz, used to synchronize data collection, and HS is the line locking system. Synchronization signal, VS is the field synchronization signal, VBLK is the field blanking signal, and FID is the odd and even field signal. The high level of HS represents 720 valid sampling points in one line, and the high level of VS represents one field of valid signals. For NTSC signals, a single field is 243 lines. When the odd and even field signal FID is "1", it means that the current field is an odd number. , "0" indicates an even number field.

Image storage module
　　In order to achieve real-time collection and processing of images, it is often necessary to perform video input conversion and image processing in parallel. Traditional methods to achieve synchronization of data acquisition and processing include: using FIFO memory; using dual-port RAM; using dual/single-port RAM to alternately switch to store data. Considering that the image processing system needs to process a large amount of data and the price of FIFO memory and dual-port RAM, this design uses a high-speed dual/single-port SRAM to alternately switch to store data. The image capacity of one frame is 720×486=349.92K pixels, and 512K×8bit high-speed SRAM is used. TVP5146's sampling frequency for brightness signals is 13.5MHz, and the data interval between two writes is 74ns. You can choose Cypress's CY7C1049CV33 (512K×8bit, 12ns, 3.3V) to complete data storage.

　　The switching between the two frames is automatically realized by the frame memory controller designed by CPLD. When frame A stores the data output by TVP5146, DSP reads and processes the data of frame B, and sends it to the liquid crystal display after completing the processing. After frame A is filled with one frame of data, and the processor has also processed frame B data and completed one frame of image display, the ping-pong switch constructed by CPLD switches the two interfaces, and DSP begins to read data from frame A for processing. In this way, The two frames are rotated, realizing parallel operations of acquisition, processing and display.

　　This design uses the occasion parallel method to write the data of two fields into a frame memory. The system uses the VS signal to control this. When the VS signal is valid, it indicates that a new field has started. At this time, the invalid line counter starts to work and controls the image lines that do not need to be collected. After counting to the threshold, the valid line counter starts to work, controls the image lines to be collected, and issues High-order address signal A[18..11]; Similarly, when HS is valid, the invalid pixel counter starts to count the invalid pixels in each row, and then the valid pixel counter starts to count the rows of valid pixels that need to be collected; each time it counts up to 720 pixels After that, wait for the arrival of the next valid row signal, and at the same time increase the valid row counter by 1. Since the frame memory capacity selected by the system is large, A10 uses the inverted signal of the FID as the frame memory address to provide 1024 storage spaces for each line of images (720 are actually used), which can simplify data writing and reading. Control circuit. The interlaced video signal will be stored line by line in the frame memory.

　　Figure 3 shows the CPLD programming to form the frame memory and video acquisition controller. The video acquisition controller internally generates the address signal A[18:0], the write signal WR and the frame switching signals RDY1 and RDY2 of the frame memory based on the synchronization signals DATACLK, HS and VS of the TVP5146. The frame memory controller performs interface conversion according to the switching signals RDY1 and RDY2: when a frame of image is stored in the frame memory, RDY1, one of the two necessary conditions for frame switching, is set to high level, and RDY2 processes a frame of image and sends it out after the DSP The display post-set is high level. When both are true at the same time, the connection of the two channels is switched to start a new round of image processing process. At the same time, RDY1 and RDY2 are reset to prepare for the next switch.

　　The external SDRAM of TMS320C6146DSK has a total capacity of 4M×64bit, which is 2 pieces of MT48LC2M32B2. It is used as a buffer for video data before being sent to the LCD after DSP processing.

Image display module
　　This design uses EPSON's E35G23 graphics display module, 320×240 pixels, with row and column drive circuits and backlight circuits, and 16-level grayscale display. The system uses CPLD to form a liquid crystal display controller, and uses CPLD to generate frame synchronization signals and scan clock signals. VFRAM is the frame synchronization signal, marking the start of a new frame of image on the LCD screen. Each frame contains 240 VLINE signals. After the frame mark signal VFRAM is valid, the row synchronization signal is generated, the data buffer is read, and the data is written to the LCD under the control of the pixel clock VCLK. Each row contains 320 VCLK signals to complete the writing of one frame of data.

Conclusion
　　This article uses high-speed DSP TMS320C6416 as the core processor, uses TVP5146 to complete the digital conversion of analog video signals, CPLD completes the timing control of the system, and uses dual/single-port SRAM to alternately store the collected video data. After the DSP processes the data, it is sent to the SDRAM cache. Finally, the data is read out from the cache and sent to the LCD screen for display, realizing real-time collection, processing and display of video data. This system is designed based on vehicle video surveillance and will play a good role in reducing traffic accidents.