Research and Implementation of 8PSK Soft Demodulation Based on FPGA

Abstract: The principle of 8PSK soft demodulation is first analyzed. In view of the high computational complexity of the optimal log-likelihood ratio (LLR), a relatively simplified maximum (MAX) algorithm is selected as the implementation scheme for the field programmable gate array (FGPA) hardware platform. Subsequently, the 8PSK soft demodulator is designed and implemented in the hardware description language (VHDL) and functionally simulated on the QUARTUS II simulation platform, and the final test is completed on the Stratix II series FPGA chip of Altera by cascading with the LDPC decoding module. By comparing with the MATLAB simulation results, the correctness and feasibility of the simplified 8PSK soft demodulator design are verified.

0 Introduction

With the development of satellite communication service industry, people have higher and higher requirements for service quality. In 2003, the satellite digital video broadcasting (DVB-S2) system adopted the efficient low-density parity check code (LDPC), which improved the bandwidth efficiency by about 30%. As we all know, satellite communication systems often use LDPC and BCH cascaded forward error correction coding to obtain higher performance. In order to achieve this performance requirement, soft demodulation is required in the demodulation part of the received signal. Therefore, in high-order modulation systems (such as 8PSK), a suitable, simple and easy-to-implement soft demodulation technology is required to demap the received signal. In the design of traditional wireless communication systems, the log-likelihood ratio (LLR) algorithm is often used in soft decision technology as the optimal performance algorithm. However, due to the high complexity of the algorithm, it involves multiple logarithmic and exponential operations and is not suitable for hardware implementation. Therefore, many simplified soft decision algorithms have emerged one after another. Among them, the maximum value (MAX) algorithm simplifies the exponential and logarithmic operations based on the LLR algorithm. Its hardware implementation complexity is greatly reduced compared with the LLR, and the performance loss is smaller than that of the LLR algorithm. Therefore, in the hardware design of communication systems, the MAX algorithm is usually selected as a suitable soft demodulation algorithm to soft-demodulate the received signal.

Here, we first analyze the complexity of the 8PSK soft demodulation algorithm and the basic principles of the MAX algorithm, and implement this soft demodulation hardware module on Altera's Stratix II series FPGA chip, and jointly verify it with the LDPC decoding module. The software and hardware verification and analysis show that this design achieves a good compromise in terms of computational complexity, throughput, and final bit error performance.

1 8PSK soft demodulation principle

The modulation constellation diagram of 8PSK is shown in Figure 1. Each symbol represents three bits. Formula (1) represents the probability density function of the received signal after passing through the Gaussian white noise channel. Formula (2) describes the value of each constellation point on the constellation diagram. Si represents 1 to 8 constellation points on the constellation diagram.

Figure 1 8PSK modulation constellation

Where σ is the standard deviation of the Gaussian white noise channel. Using the LLR algorithm, the soft decision is shown in equation (3), where the terms in the numerator represent the sum of the probabilities that the bit is 0, and the terms in the denominator represent the sum of the probabilities that the bit is 1.

From equations (2) and (3), it can be seen that each calculation of one bit of LLR requires square, exponential and logarithmic operations. Therefore, the LLR algorithm has high computational complexity and large resource overhead, especially the high exponential and logarithmic complexity of hardware implementation. Therefore, the LLR algorithm is not suitable for FPGA implementation. The maximum value (MAX) algorithm can effectively avoid the exponential and logarithmic operations of calculating the log-likelihood value of each bit. Its principle is shown in equation (4).

From equations (3) and (4), the simplified MAX algorithm is shown in equation (5). From equations (3) and (5), it can be seen that it is difficult to implement exponential and logarithmic operations of the LLR algorithm in hardware, while the MAX algorithm only requires simple addition and subtraction operations and a few multiplication operations, which is easy to implement in engineering hardware. Therefore, the MAX algorithm is selected as the final solution for hardware implementation.

2 Algorithm Performance Analysis

The following performance simulation comparison analysis was performed using the MATLAB simulation platform.

A set of random sequences is generated by MATLAB, with a length of 100,000 coding blocks, each coding block is 4,032 bits, and then passes through the LDPC coding module with a code rate of 1/2. Through the corresponding 8PSK modulation, the logarithmic likelihood ratio is calculated by the LLR optimal algorithm, floating-point MAX algorithm, and fixed-point MAX algorithm in the range of Eb/N0 of 4 dB to 7 dB, and finally passes through the LDPC decoding module to obtain the error performance.

Table 1 is the bit error rate corresponding to each Eb/N0 calculated by the MATLAB simulation platform, and Figure 2 is the corresponding bit error rate curve. As shown in Figure 2, for any test point in the Eb/N0 test interval of 4 dB to 7 dB, the bit error rate of the LLR optimal algorithm is always smaller than that of the fixed-point MAX algorithm and the floating-point MAX algorithm, among which the floating-point MAX algorithm has a medium bit error performance and the fixed-point MAX algorithm has the worst. The MAX algorithm reduces the bit error performance in exchange for a reduction in computational complexity, and its bit error performance is worse than that of the LLR optimal algorithm. Compared with the floating-point MAX algorithm, the fixed-point MAX algorithm truncates and limits the I and Q signals of the input soft demodulation module and the likelihood ratio of the output, respectively. As shown in Figure 2, the fixed-point MAX algorithm loses a certain bit error performance relative to the floating-point MAX algorithm. It can be seen from the table that when Eb/N0 is 6.64 dB, the bit error rate of the fixed-point MAX algorithm is 6.5125×10-8, which verifies that the fixed-point solution can meet the system design requirements.

Table 1 MATLAB bit error rate simulation table

Figure 2 MATLAB bit error rate simulation

3 MAX Algorithm Hardware Implementation

Since the hardware implementation is fixed-point operation, the implementation of the MAX algorithm is designed for the hardware of the fixed-point MAX algorithm. The hardware simulation flow chart is shown in Figure 3. First, MATLAB is used to generate a random sequence. Assuming that each coding block is 4032 bits and the LDPC coding efficiency is 1/2 code rate, each coding block is 8064 bits after LDPC coding. After 8PSK modulation into symbols, each coding block is modulated into 2688 symbols, and the real and imaginary parts are divided into I and Q paths, and then Gaussian white noise with a signal-to-noise ratio of SNR is superimposed. Finally, the data file is stored in RAM. In hardware implementation, the fixed-point MAX soft demodulation module reads data from the RAM at a certain rate and performs soft demodulation. The log-likelihood ratio of the soft demodulation output is stored in the ping-pong RAM. Every time a coding block is full, a read valid signal is sent to the LDPC decoder. The LDPC decoder starts to read the log-likelihood value of the entire coding block at a certain rate in the next clock cycle after receiving the valid signal, and then starts LDPC decoding, and finally outputs the final decoding result at a certain rate.

Figure 3 Hardware design simulation

4 Analysis of Hardware Design Results

To verify the performance of a soft demodulation module, it is necessary to cascade the decoding module for simulation and synthesis verification. In hardware design, the MAX fixed-point algorithm module and the LDPC decoding algorithm module are cascaded on the Stratix II FPGA hardware platform, and then the integrated wiring is performed, and finally downloaded to the hardware platform for testing.

Use Chipscope to add observation sampling signals, trigger signals and signals to be observed to the engineering files that have passed the simulation, and then re-synthesize, layout and route to generate bit files. After downloading to the target board, use Chipscope for online testing, and verify the correctness of the design by comparing the output results with the input bit stream. Analyzing the QUARTUS II synthesis report, the design module only needs adders and subtractors, some registers and 16 multiplication modules, which uses fewer resources and can meet the design requirements of low complexity and high throughput.

5 Conclusion

Since the LLR algorithm has a high computational complexity and is not easy to implement in hardware, the simplified MAX algorithm avoids exponential and logarithmic operations, greatly reducing the computational complexity, and only requires addition, subtraction and a few multiplication operations, which is suitable for hardware implementation. The design verifies the accuracy of the MAX soft demodulation algorithm hardware design through MATLAB and VHDL simulation comparison. At the same time, the module is cascaded with the LDPC decoding module and runs on a specific FPGA chip, and the feasibility of the design is further verified using the on-chip analyzer Chipscope.