How to reduce power consumption when using FPGA for design

Nowadays, various specifications and standards have put forward increasingly stringent requirements on the overall power consumption of the system , so that system designers are facing increasingly daunting challenges.

Traditionally, ASICs and CPLDs have been the clear winners in the low-power race. However, due to their relatively high cost and increasing user requirements for high-end performance and additional logic, the use of CPLDs in low-power applications is losing its edge. ASICs are also facing the same risks. Increasingly, programmable semiconductor devices such as FPGAs are becoming a popular solution.

When starting to create a new design, bill of materials, cost, power consumption, board size, and time to market are all factors that need to be carefully considered. After prioritizing the initial requirements, designers need to consider a variety of factors before selecting an FPGA for system design.

should

1. List the key points of your design. Consider how long the FPGA can run at high speed, low speed, or when the clock is stopped? Also consider if the device sleeps for a long time, then can burst mode processing at a higher clock frequency achieve the required throughput? Is it a better choice to let the design run longer at a lower clock frequency? For this process, FPGA vendors provide auxiliary tools for power analysis and prediction, but the analysis results of some tools are too optimistic than the actual situation.

2. Calculate power consumption for each product state. To calculate power consumption in all states covering the entire product life cycle or expected battery operating time, consider multiple states such as power-on, standby, idle, dynamic, and power-off. An FPGA used in a user handheld device with Wi-Fi communication function may be in working mode only 5% of the time, static for another 20% of the time, and standby for 75% of the time.

Calculate worst-case static power consumption. Newer FPGA technologies may have higher static power consumption than the designer imagines, especially over temperature. Make sure to account for the core, I/O, and any auxiliary supplies. When calculating static power consumption, apply P=IV to each component.

3. Analyze the expected temperature and voltage changes. The entire product power consumption analysis process should be covered. The heat and voltage changes during product operation need to be calculated.

4. Estimate the battery operating time under each operating mode of the system (such as short-term high-performance operation and long-term low-performance operation) to determine the best option.

Figure: Unlike other semiconductor devices, FPGAs have some unique power characteristics.

Should not

1. Forgetting to consider factors when using low-power modes. Some power-saving modes require board size considerations when implementing them, so the design should be able to accommodate this. Some modes are not suitable for use because the implementation process is too complex and requires an unacceptably long wait time when the device enters or leaves a certain mode. For example, the low-power modes provided by SRAM or SRAM hybrid FPGAs require device reconfiguration, at which time the power consumption can surge to 1W.

2. Allowing user static RAM and high I/O voltages to draw too much power. When creating clock regions using local or regional clock sources, use “enabled” logic to mask clock changes in the system. User static RAM may draw too much power, so choose a technology that uses less RAM. I/Os also draw a lot of power, so low-voltage TTL standards and lower I/O voltages are recommended. Using serial low-voltage differential signaling for chip-to-chip data transfer saves more power than off-chip parallel buses, which can be implemented using double data rate registers. Further examine whether components can be integrated or functions can be streamlined, and larger FPGAs can accommodate microcontroller soft cores, all of which can save power.

3. Relying only on measured power numbers. Perform calculations based on theoretical and power simulator numbers, and understand how those numbers were derived. Do those numbers account for silicon variations? Remember that what you measure on a platform today may not be what a low-power device shipping tomorrow will actually do. So be careful when calculating power based only on measured data.

4. Omitting power consumption values ​​for additional components. Sometimes implementing a solution with a certain FPGA technology may require additional components. For example, a self-booting design may require memory, while a non-volatile FPGA can provide a monolithic implementation.