WCDMA system: Research on an effective WCDMA channel coding and decoding task scheduling scheme

Abstract: According to the requirements of WCDMA multi-channel multiplexing, high-speed services and terminal systems in terms of power consumption, performance, volume, etc., a solution based on slot scheduling of each sub-processing unit in the channel encoding and decoding module is proposed, which can optimize the resource allocation of the entire module and improve the execution efficiency. Considering the outstanding performance characteristics of DSP processors and large-scale FPGAs, this paper adopts DSP and FPGA collaborative processing to implement the entire solution.

Keywords: WCDMA; channel codec; time slot; DSP; FPGA; interrupt;

0 Introduction

WCDMA supports high-speed transmission and can also multiplex services with different speed and quality requirements. This requires the channel coding and decoding module to adopt a flexible service multiplexing scheme to efficiently and dynamically process multiple channels[1]. However, due to the particularity of terminal equipment in terms of power consumption, real-time performance, and storage requirements, the implementation of the entire system becomes more complicated.

With the rapid development of DSP processors and large-scale FPGA technology in recent years, the hardware architecture of DSP+FPGA can fully support the implementation of these complex technologies [1]. However, since the hardware architecture requires corresponding software support to exert its performance, seeking an effective software solution is the key to realizing the entire channel coding and decoding module. In this paper, combined with the characteristics of WCDMA one frame with multiple time slots [3], a time slot-based interrupt task processing solution is proposed to flexibly schedule each processing module. This solution gives full play to the advantages of DSP in real-time task scheduling, maximizes the use of the hardware resources of the entire system, improves the execution efficiency as much as possible, and effectively reduces the system power consumption to a certain extent.

1 Description of WCDMA terminal side channel coding and decoding

The terminal side channel coding and decoding module includes an uplink coding multiplexing link and a downlink decoding multiplexing link.

According to the 3GPP TS25.212 protocol [4], the process of uplink multiplexing and channel coding in the WCDMA system is as follows: the transport block is channel-coded after CRC check, the coded data is interleaved and rate-matched for the first time, and then the data of multiple transport channels is multiplexed and interleaved for the second time, and finally mapped to the corresponding physical channel. If multi-code transmission is performed, the data of the physical channel needs to be segmented after the transport channel is multiplexed.

Each data block set is attached to the time interval (TTI) from the upper layer to the transmission channel. The channel coding and decoding module calculates the processing parameters for each link from CRC to rate matching based on the TFI information. When multiple transmission channels are multiplexed to the physical channel, the physical layer sorts the TFI information of different transmission channels to obtain the transmission format combination (TFCI), which describes the multiplexing relationship of each transmission channel. At the same time, the data of multiple transmission channels that have been rate matched are serially multiplexed according to the TFCI to form a coded composite transmission channel (CCTrCH), and the CCTrCH is mapped to the physical channel after the second interleaving.

The decoding multiplexing chain of the downlink is roughly the same as the multiplexing chain of the uplink, except that for each encoding module of the uplink, the downlink provides a corresponding inverse processing module. The difference from the uplink is that the rate matching module and the wireless frame merging module are located in different positions from the uplink, and DTX processing with fixed or variable bit positions is added.

2 Research on task scheduling based on time slots

The time slot-based task scheduling scheme proposed in this paper is based on the DSP+FPGA hardware architecture. DSP realizes the control and scheduling of tasks, and FPGA completes the specific implementation of each processing submodule, and these modules are shared by each channel.

2.1 Principle description of time slot-based task scheduling scheme

According to the protocol description of WCDMA channel coding and decoding, the information flow is divided into multiple transmission blocks and sent and received in units of TTI cycles. The processing of the entire information flow is completed by the DSP based on the received interrupt triggering different tasks. In this scheme, two DSP interrupts are used: one is the slot interrupt with an interrupt cycle of 667us; the other is the frame interrupt with an interrupt cycle of 10ms. The two interrupts have different priorities, and the slot interrupt has a higher priority than the frame interrupt. The task scheduling scheme based on the slot in this paper uses these two interrupts as a reference to periodically locate the slot tasks.

The main task of the time slot interrupt is to divide 10ms into 15 equal parts through interrupt triggering. Each interruption schedules the operation of different functional sub-modules in the FPGA according to different links of the uplink and downlink encoding and decoding process. For the functional sub-modules that cannot be completed within a 577us time, their running status is monitored to control the operation of the entire process. The task of the frame interrupt is to periodically divide a TTI cycle into 10ms frames through interrupt triggering.

2.2 WCDMA terminal side codec module execution mechanism

The time slots occupied by each stage of uplink coding in a channel with a TTI period of 10ms are shown in Table 1. The channel coding parameters required for the TTI period are determined in slot 0, and the Turbo or convolutional coding parameters and rate matching parameters are calculated from the semi-static parameters and dynamic parameters of the transmission format.

Table 1 Time slot allocation of uplink coding link process on WCDMA terminal side

Slot 1-Slot 11 performs convolutional coding or Turbo coding on multiple channels. Multiple channels share the Turbo encoder and convolutional encoder. The DSP queries the encoder status in each slot interrupt. When an encoder is idle and a channel needs to be encoded, the DSP schedules the encoder to serve the channel.

Slot 12-slot 13 performs the first interleaving and rate matching. The first interleaving has three independent modules, which can interleave three channels at the same time. The DSP controls the use according to the processing flow of each channel.

Slot 14 performs CCTrCH multiplexing and the second interleaving.

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When the uplink transmission channel TTI is not equal to 10ms, the uplink processing flow changes slightly. The first frame in the TTI performs the relevant flow actions according to Table 1. In the frames after the TTI, since the CRC check and Turbo coding or convolutional coding have been completed in the first frame, only the first interleaving and rate matching, and the second interleaving and channel multiplexing are required.

In a downlink with a TTI of 10ms, the time slots occupied by each decoding stage are allocated as shown in Table 2. The execution scheduling mechanism of each time slot is similar to that of the uplink coding link.

Table 2 Time slot allocation for downlink decoding link process on WCDMA terminal side

When TTI is not equal to 10ms, parameter calculation and memory allocation must be performed in the first frame of the TTI, and then the second deinterleaving and channel demultiplexing, the first deinterleaving and rate matching are performed in the first few frames of the TTI. Viterbi decoding or Turbo decoding, CRC check and data output are performed in the last frame of the TTI.

During the whole process of parallel processing of uplink and downlink, since each sub-processing unit is implemented by FPGA modularization, the DSP will shut down the clock of the sub-modules that are not called at a certain moment, making them in a dormant state. When they are called again, the DSP will restart the clock. This reduces the system power consumption by saving the execution time of each module.

3 Solution Implementation and Performance Testing

In the implementation process, we use a DSP processing chip with TEAK[5] as the core. This is conducive to the integration of the final ASIC. In addition, as a 32-bit processor, it has flexible and diverse addressing modes and provides huge processing power. The FPGA uses Xilinx's VirtexII XC2V6000[6], which has rich resources and powerful input and output capabilities.

According to the process structure and execution mechanism proposed by this scheme for this system, this paper lists the data processing flow chart of the uplink (see Figure 1). According to the characteristics of uplink data processing, the entire uplink channel decoding process is divided into three main links: convolutional coding or TURBO coding, first interleaving and second interleaving. The data blocks processed by CRC are input to the convolutional encoder or TURBO encoder according to the TFCI encoding method; the encoded data is written into the first interleaver input buffer. The first interleaver has 3 independent modules and can interleave three transmission channels at the same time. The multiplexing of CCTrCH is completed in the process of writing data from the first interleaving output buffer to the second interleaving input buffer.

Figure 1 WCDMA terminal side channel coding and decoding uplink signal flow diagram

FPGA completes the implementation of each specific module in channel decoding, and each functional module provides a corresponding control interface. DSP configures parameters and schedules tasks for each hardware module through these control interfaces, thereby controlling the decoding process of multiple downlink transmission channels, and can schedule each functional module to serve multiple transmission channels to the maximum extent, so that each functional module can be shared by multiple transmission channels, improving the ability to process multiple downlink channels at the same time. The entire process fully considers the advantages and disadvantages of DSP and FPGA, and improves the performance of the entire system through the mutual cooperation and collaborative processing of software and hardware.

The downlink is similar to the uplink. The DSP completes the task scheduling and module configuration, and the FPGA completes the specific implementation of each downlink decoding sub-module.

Finally, we multiplexed the two services to implement the loopback test of the platform. The entire platform connects the second interleaving output buffer of the uplink with the second deinterleaving input buffer of the downlink to achieve the loopback of the uplink coding link and the downlink decoding link. One of the two services is a low-rate voice service with a rate of 12.2kbps, a TTI of 20ms, and convolutional coding; the other is a high-rate service with a rate of 384kbps, a TTI of 10ms, and Turbo coding. The entire test process lasted for two hours. The result was that the voice loopback sound was clear, and the high-rate data loopback test bit error rate was less than 10e-6. Such results fully met the implementation requirements specified by 3GPP.

The test shows that this solution not only meets the specification requirements in the processing of high-speed services, but also has strong adaptability to the multiplexing of different types of services, and meets the basic performance requirements of WCDMA. At the same time, due to the use of sleep processing for idle submodules during operation, the power consumption of the entire system module is greatly reduced during operation, fully considering the special requirements of mobile terminals.

4 Conclusion

By flexibly scheduling the processing submodules in each link of service multiplexing, the time slot-based task scheduling scheme proposed in this paper realizes the channel encoding and decoding processing on the WCDMA terminal side. As an ASIC verification platform, using this scheme can reduce the system power consumption and increase the scalability of the module, which is more conducive to system development and maintenance.