Design of Resolution Bandwidth of Digital IF Spectrum Analyzer

Spectrum analyzers can be divided into two types according to their implementation methods: analog and digital. The former is based on analog filters, while the latter is based on digital filters and FFT analysis. In contrast, analog spectrum analyzers cannot obtain real-time spectrum, and because analog filters are affected by nonlinearity, temperature drift, aging, etc., the measurement accuracy is not high; Digital spectrum analyzers, because they are based on digital filters, have small form factors, high frequency resolution, good stability, can obtain very narrow analysis bandwidth, and have high measurement accuracy; and because they are designed based on high-speed ADC technology, digital signal processing technology, FFT analysis, etc., they have multiple spectrum analysis capabilities. With the rapid improvement of the performance of field programmable gate array (FPGA) devices, DSP devices, etc. in terms of chip logic scale and processing speed, digital spectrum analyzers have faster measurement speeds and stronger real-time performance.

In a digital IF spectrum analyzer, resolution bandwidth filtering is the key to the design of the digital IF processing module. It determines the effective signal bandwidth of the spectrum analysis and characterizes the spectrum analyzer's ability to clearly separate the two input signals in the response. It is one of the main technical indicators of the spectrum analyzer. In order to meet the real-time and accuracy requirements of the signal, the digital IF signal is usually obtained by high-speed A/D sampling, but its data rate is too high, so it becomes a bottleneck for digital processing. Generally, it is necessary to use digital orthogonal demodulation technology to move the signal to the baseband, and then use multi-rate signal processing technology to design the extraction filter to reduce the data rate and finally realize the digital FIR filter.

This paper adopts digital down-conversion technology and designs a digital intermediate frequency processing module based on FPGA hardware, calls different IP cores for design, and uses a parameter-configurable structure to implement a variable decimation rate filter and a resolution bandwidth digital filter. Since the IP core has undergone rigorous performance testing and optimization, the timing is stable, and thus it can meet the system's high-speed and real-time processing requirements.

1 Digital Down-Conversion Principle

Fully digital intermediate frequency processing technology is one of the key technologies in software radio. It is mainly used to down-convert intermediate frequency signals to baseband signals. While reducing the sampling rate, this technology can ensure that the required signals are not aliased, which is very convenient for the subsequent use of more baseband signal processing technologies. Fully digital intermediate frequency technology includes two parts: digital orthogonal demodulation technology and multi-sampling rate signal processing technology.

1.1 Digital Quadrature Demodulation

Orthogonal demodulation is also called orthogonal frequency conversion. It is mainly achieved through digital mixing. Assume that the input intermediate frequency signal is:

Among them, the signal center frequency is much larger than the signal bandwidth B, and the sampling rate of the signal satisfies the Nyquist theorem, that is, f0>>B, fs>2B. Then, after orthogonal transformation, the baseband modulation signal of the signal is:

In the formula, ZBI (t) is called the I signal and ZBQI (t) is called the Q signal. It can be seen from formula (2) that the baseband signals ZBI (t) and ZBQI (t) only contain amplitude and phase information and the frequency is zero. Therefore, the orthogonal demodulation process is the process of obtaining the baseband signal from the intermediate frequency signal x (t).

The system module of the orthogonal demodulation process is an orthogonal dual-channel structure, which is called I channel and Q channel. Since the input and orthogonal local oscillator and mixer are all digitally implemented, it has the characteristics of high integration and good consistency, and can obtain good channel consistency. The use of digitally controlled oscillators also ensures the orthogonality of the phase.

1.2 Multi-rate signal processing

Since the sampling rate of the intermediate frequency signal is high, and baseband signal processing generally only needs to be performed at a lower sampling rate, the baseband signal after digital orthogonal demodulation is in a serious oversampling state, and conversion between sampling rates must be performed to reduce the data flow rate. This change in signal sampling rate is based on multi-rate signal processing technology.

Integer multiple decimation can reduce the signal sampling rate by an integer multiple, and the decimation multiple is D. Since decimation reduces the sampling rate of the signal, the decimated signal may no longer meet the Nyquist sampling condition and produce aliasing. In order to ensure that the required signal is not distorted, before decimation, a digital low-pass filter is generally used to band-limit the signal according to the decimated sampling rate, so that the filter cutoff frequency ωc is the maximum bandwidth B of the required signal. When the sampling rate fs1 before decimation and the sampling rate fs2 after decimation meet fs2=fs1/D≥2B, no aliasing will occur after the signal is decimated.

1.3 Principle of spectrum analyzer multi-decimation rate filter

The resolution bandwidth of the digital IF spectrum analyzer is achieved through the design of multi-sampling rate filters. For the data stream that is still oversampled after down-conversion, it is necessary to filter and extract at different rates to obtain different real-time analysis bandwidths. In this way, the actual decimation rate varies greatly. For example, when a narrower resolution bandwidth is required, the decimation rate is very high, requiring multi-stage filtering and decimation to gradually reduce the sampling rate, which also reduces the requirements for each level of anti-aliasing filters. Since the ADC is sampled at the intermediate frequency, the data rate and the sampling rate are consistent, and the FIR filter cannot guarantee the design of high sampling rate and low bandwidth. Therefore, it is necessary to first use CIC (comb filter) and HB (half-band filter) filter decimators to perform large decimation to quickly reduce the data rate, and then filter by the FIR filter. Combined with orthogonal demodulation, the structural block diagram of digital down-conversion is shown in Figure 1.

Figure 1 Block diagram of digital down converter

The coefficients of CIC (comb) filters are all 1, and there are only addition operations, no multiplication operations, so the hardware implementation is very easy, and it can achieve a very high processing rate, which is very suitable for the first stage of extraction and large extraction factors in the extraction system. However, the transition band and stop band attenuation characteristics of the single-stage CIC filter are not good, and it is usually necessary to use a multi-stage cascade method to increase the filter sidelobe level attenuation. When a 5-stage cascade is selected, the stop band attenuation is about 67.3dB, which can meet the attenuation requirements of the first-stage filter. Although the CIC extraction rate is high, its frequency response 3dB effective bandwidth is very narrow. In order to ensure that the effective bandwidth remains basically unchanged and continue to reduce the extraction rate, a half-band filter can be used in the subsequent stage.

Almost half of the coefficients of the HB (half-band) filter are zero, and the amount of computation during filtering can be reduced by half. Its decimation factor is fixed at 2, so after passing through N-stage HB filters, the sampling rate can be reduced by 2N times. The frequency response after multi-stage filtering and decimation has no overlap in the passband, and it only has intersections at the edge of the transition band, so it has a good anti-aliasing effect.

Through filtering and extraction of CIC and HB multi-group filters, the baseband signal is reduced to a lower sampling rate, which is suitable for FIR processing.

Since the FIR filter has a high order, it can be designed to have a frequency response with a small transition band, high stopband attenuation and a good shape factor to meet the special requirements of the spectrum analyzer for the resolution bandwidth filter.

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2 Digital IF Processing Logic

In recent years, with the rapid development of FPGA devices in terms of process and logic scale and the continuous reduction of costs, the use of FPGA devices to implement high-speed professional digital down-conversion modules has become a common method in system design. FPGA chips not only integrate a large number of programmable logic resources, but also contain a wealth of hard-core and solid-core resources for digital signal processing, so they can meet the digital applications and designs of various systems. In addition, they have rich IP core resources, are flexible and fast to implement, have stable performance, and can meet high-speed timing requirements.

FPGA IP core is a pre-designed functional module, which generally adopts a parameter-configurable structure and can be called through the Core Generator tool. The design of digital down-conversion can be implemented by using the numerically controlled oscillator (NCO) and multiplier of orthogonal digital demodulation, and respectively calling the IP core DDS Compiler 4.0 and Multiplier 11.2, where DDS Compiler can provide two channels, SINE and COSINE. In the extraction filter design, the multiple groups of filters shown in Figure 1 can be implemented by calling IP cores (CIC Compiler 1.3 and FIR Compiler5.0). CIC Compiler 1.3 can provide input data sampling rate, operating frequency, and programmable extraction. Multiple parameter settings; HB filters and FIR filters both use FIRCompiler 5.0. The IP core can import filter coefficients in *.coe format and distinguish different types of filters by importing different coefficients. It also provides settings for different filter structure types, including multiply-accumulate structures, DA algorithm-based structures, and polyphase filter structures, as well as settings for basic filter parameters such as input data sampling rate and operating frequency.

The overall design of the digital down-conversion module is shown in Figure 2. Since the I and Q paths are symmetrical, for convenience, only the digital down-conversion implementation process of the Q path is described here. This design is implemented using Xilinx's Spartan-3A-DSP series FPGA chip, which integrates the DSP48A module and contains rich multiplier resources, suitable for the implementation of digital signal processing modules, and has low cost and power consumption.

Figure 2 Overall design of digital down-conversion module

The processing module can realize orthogonal demodulation, extraction filtering and FIR filtering in sequence according to the principle of digital down-conversion, and finally obtain the baseband signal. The module has three inputs. The signal input is the output sequence of the A/D converter, with a bit number of 14-bit, a sampling rate of 100MSPS, and a center frequency of 21.4MHz. This determines that the output bit number of the NCO in the digital intermediate frequency can be set to 14-bit and the output frequency can be set to 21.4MHz.

The clock input is the accompanying clock of the A/D converter output sequence, with a frequency of 100MHz, which can be used as the working clock of the processing module.

In the ISE of the FPGA design platform, BUFG is a global buffer, which is connected to the dedicated clock resources in the chip. The purpose is to reduce the transmission delay of the signal and improve the driving ability, which is very important for the key clock signal in the timing circuit. DCM is a digital clock management unit with minimal clock delay and jitter, so the DCM+BUFG method can be used to distribute the clock input as the FPGA clock. Using global clock resources can ensure timing synchronization.

The bandwidth input is a resolution bandwidth step input, which determines the bandwidth B (RBW) to be analyzed and the decimation of the filter bank. During operation, the 3dB bandwidth and input sampling rate of the last FIR filter can be determined by the bandwidth to be analyzed, and then the CIC filter decimation factor and the number of HB filter cascades are determined according to the ratio of the A/D sampling rate to the FIR input sampling rate.

In addition, in the overall design of the module, bit processing is also a key, which is determined by the bandwidth step input and can adjust the binary output bit width of each part. Because the convolution operation of the filter is a multiplication and accumulation operation, this will lead to an increase in the output bit number of the filter. When the output precision and accuracy meet the requirements, bit processing can be performed after orthogonal demodulation and each level of filter. This method is to prevent the accumulation of excess output bits in the post-stage filter, thereby saving FPGA logic resources; secondly, it is to adjust the output amplitude of the filter group to avoid inconsistent output amplitude when different bandwidths are selected.

3 Resolution Bandwidth Design

The resolution bandwidth of this design ranges from 1kHz to 3MHz, and is changed in steps of 1-3-10, with a total of 8 gears. The resolution bandwidth step input is listed in Table 1. Each step determines the corresponding CIC decimation factor and the number of HB cascades, and also determines the input data and corresponding sampling rate of the last FIR filter.

Table 1 Decimation factor allocation table (sampling rate 100MSPS)

2 Digital IF Processing Logic

In recent years, with the rapid development of FPGA devices in terms of process and logic scale and the continuous reduction of costs, the use of FPGA devices to implement high-speed professional digital down-conversion modules has become a common method in system design. FPGA chips not only integrate a large number of programmable logic resources, but also contain a wealth of hard-core and solid-core resources for digital signal processing, so they can meet the digital applications and designs of various systems. In addition, they have rich IP core resources, are flexible and fast to implement, have stable performance, and can meet high-speed timing requirements.

FPGA IP core is a pre-designed functional module, which generally adopts a parameter-configurable structure and can be called through the Core Generator tool. The design of digital down-conversion can be implemented by using the numerically controlled oscillator (NCO) and multiplier of orthogonal digital demodulation, and respectively calling the IP core DDS Compiler 4.0 and Multiplier 11.2, where DDS Compiler can provide two channels, SINE and COSINE. In the extraction filter design, the multiple groups of filters shown in Figure 1 can be implemented by calling IP cores (CIC Compiler 1.3 and FIR Compiler5.0). CIC Compiler 1.3 can provide input data sampling rate, operating frequency, and programmable extraction. Multiple parameter settings; HB filters and FIR filters both use FIRCompiler 5.0. The IP core can import filter coefficients in *.coe format and distinguish different types of filters by importing different coefficients. It also provides settings for different filter structure types, including multiply-accumulate structures, DA algorithm-based structures, and polyphase filter structures, as well as settings for basic filter parameters such as input data sampling rate and operating frequency.

The overall design of the digital down-conversion module is shown in Figure 2. Since the I and Q paths are symmetrical, for convenience, only the digital down-conversion implementation process of the Q path is described here. This design is implemented using Xilinx's Spartan-3A-DSP series FPGA chip, which integrates the DSP48A module and contains rich multiplier resources, suitable for the implementation of digital signal processing modules, and has low cost and power consumption.

Figure 2 Overall design of digital down-conversion module

The processing module can realize orthogonal demodulation, extraction filtering and FIR filtering in sequence according to the principle of digital down-conversion, and finally obtain the baseband signal. The module has three inputs. The signal input is the output sequence of the A/D converter, with a bit number of 14-bit, a sampling rate of 100MSPS, and a center frequency of 21.4MHz. This determines that the output bit number of the NCO in the digital intermediate frequency can be set to 14-bit and the output frequency can be set to 21.4MHz.

The clock input is the accompanying clock of the A/D converter output sequence, with a frequency of 100MHz, which can be used as the working clock of the processing module.

In the ISE of the FPGA design platform, BUFG is a global buffer, which is connected to the dedicated clock resources in the chip. The purpose is to reduce the transmission delay of the signal and improve the driving ability, which is very important for the key clock signal in the timing circuit. DCM is a digital clock management unit with minimal clock delay and jitter, so the DCM+BUFG method can be used to distribute the clock input as the FPGA clock. Using global clock resources can ensure timing synchronization.

The bandwidth input is a resolution bandwidth step input, which determines the bandwidth B (RBW) to be analyzed and the decimation of the filter bank. During operation, the 3dB bandwidth and input sampling rate of the last FIR filter can be determined by the bandwidth to be analyzed, and then the CIC filter decimation factor and the number of HB filter cascades are determined according to the ratio of the A/D sampling rate to the FIR input sampling rate.

In addition, in the overall design of the module, bit processing is also a key, which is determined by the bandwidth step input and can adjust the binary output bit width of each part. Because the convolution operation of the filter is a multiplication and accumulation operation, this will lead to an increase in the output bit number of the filter. When the output precision and accuracy meet the requirements, bit processing can be performed after orthogonal demodulation and each level of filter. This method is to prevent the accumulation of excess output bits in the post-stage filter, thereby saving FPGA logic resources; secondly, it is to adjust the output amplitude of the filter group to avoid inconsistent output amplitude when different bandwidths are selected.

3 Resolution Bandwidth Design

The resolution bandwidth of this design ranges from 1kHz to 3MHz, and is changed in steps of 1-3-10, with a total of 8 gears. The resolution bandwidth step input is listed in Table 1. Each step determines the corresponding CIC decimation factor and the number of HB cascades, and also determines the input data and corresponding sampling rate of the last FIR filter.

Table 1 Decimation factor allocation table (sampling rate 100MSPS)

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The purpose of decimation filtering is to reduce the high-rate baseband signal after orthogonal demodulation to a suitable signal rate for use with commonly used baseband processing techniques. Here, the relationship between the baseband signal sampling rate and the resolution bandwidth step is set to 5 times to calculate the corresponding I and Q baseband signal sampling rates, and then determine the total decimation rate of the processing module. Since the decimation rate parameter of the IP core can only be an integer, the proportional relationship between RBW and the baseband signal sampling rate should be met as much as possible by rounding the ideal decimation rate. For low decimation rate gears, it can be completed only through CIC decimation, but the HB filter must be bypassed, that is, the HB cascade decimation is 1. Through filter bypass control and programmable decimation factors, a wide range of decimation factors can be adjusted, thereby controlling data stream sampling, and variable sampling rate control of the analysis bandwidth can also be achieved.

In the overall design block diagram shown in Figure 2, the CIC filter is the first stage of the decimation part, which can achieve high-speed decimation, but its passband and stopband characteristics are not very controllable. Parameters such as the decimation rate (R) and the number of stages (N) can be set through the IP core, and the operation is simple.

The HB filter is the second stage of the extraction part. The single-stage extraction factor is fixed to 2. There are two cases of 3-stage cascade and 5-stage cascade. Each stage adopts the normalized frequency design method to avoid repeated design. The FDATOOL tool of MATLAB is usually used to design the filter, and 2 times the sampling rate of the RBW filter input signal is used as the normalized reference frequency, while ensuring that the signal within the passband frequency range of the FIR filter is not attenuated. Since the passband of the FIR filter is set to 0.2, and the HB filter is mainly used as an extraction filter, the upper limit of the passband frequency is set to 0.21, and the filter order is 19. Figure 3 shows the frequency response curve of the half-band filter (HB). The half-band filter coefficients are symmetrical coefficients and nearly half of the coefficients are zero. Only 6 of the 19 filter coefficients are involved in the multiplication calculation, so it will not consume a lot of multiplier resources. In addition, the data flow rate of the I and Q channels of the extraction part is relatively high, so the multiplication-accumulation structure is used to build the HB filter to meet the high-speed timing processing requirements.

When designing the RBW filter corresponding to each resolution bandwidth step input, in order to save FPGA logic resources and simplify the design, the normalized frequency design method can also be used, so that an RBW filter can be designed for each I and Q branch. Since the larger the input sampling rate fs of the FIR filter, the higher the minimum order of the filter, the frequency response of the filter is designed by selecting the 3dB bandwidth and the sampling rate at a normalized ratio of 0.2, and the FIR filter does not perform extraction, and its input sampling rate is equal to the sampling rate of the I and Q baseband signals. According to the normalized bandwidth of 0.20 of the I and Q signals, the upper limit of the passband frequency of the RBW filter can be set to 0.20, the lower limit of the stopband frequency can be set to 0.29, the filter order is 47, the stopband attenuation is 60dB, the waveform factor SF60/3 =B60dB/B3dB =0.29/0.20≈1.45, and the frequency response curve of the FIR filter is shown in Figure 4.

The generated filter coefficients in *.coe format can be imported into the IP core called in the FPGA. Considering the limited FPGA multiplier resources and the reduced data rate of the input data after previous extraction, the DA algorithm structure is used to build the RBW filter.

Figure 3 Half-band filter (HB) frequency response

Figure 4 Resolution filter (FIR) frequency response

4 Conclusion

The application method of using FPGA hardware and calling various IP cores to realize the full digital intermediate frequency technology has stable timing performance and can well meet the requirements of high-speed and real-time signal processing. In the design of the resolution bandwidth of the spectrum analyzer, combined with the programmable analysis bandwidth ranging from 1kHz to 3MHz, multi-rate signal processing technology can be used to reduce the sampling rate of digital signals and prepare for the spectrum analysis of subsequent signals such as digital amplitude/phase detection, video detection, DSP development, and FFT. This digital intermediate frequency processing module can also be applied to other designs such as network analysis, communication analysis, radar signal analysis, etc., and can effectively reduce the system volume and ensure the reliability of the design.