Signal Integrity and Electromagnetic Compatibility Design of High-Speed ​​Digital Circuits

introduction

Looking at the development of the electronics industry, in 1992 only 40% of electronic systems operated above 30 MHz, and most devices used DIP, PLCC and other large-volume, few-pin packages; by 1994, 50% of designs had reached a frequency of 50 MHz, and more and more devices used PGA, QFP, RGA and other packages; after 1996, high-speed design has accounted for an increasingly larger proportion of the entire electronic design field, and systems above 100 MHz can be seen everywhere. Devices using various BGA packages such as CS (wire-bonded chip-level BGA), FG (wire-bonded pin-dense BGA), FF (flip-chip small-pitch BGA), BF (flip-chip BGA), and BG (standard BGA) have emerged in large numbers. These small-volume packages with hundreds or even thousands of pins have been increasingly used in various high-speed and ultra-high-speed electronic systems.

From the perspective of the development and packaging of IC chips, the chip size is getting smaller and smaller, and the number of pins is increasing; at the same time, due to the development of IC technology in recent years, its speed is also getting higher and higher. This brings a problem, that is, the reduction in the size of electronic design leads to a larger layout and wiring density of the circuit, while the frequency of the signal is still increasing, making how to deal with high-speed signal problems a key factor in the success of a design. With the rapid increase in logic complexity and clock frequency in electronic systems, signal edges are becoming steeper, and the influence of trace interconnection and board layer characteristics of printed circuit boards on the electrical performance of the system is becoming more and more important. For low-frequency design, the influence of trace interconnection and board layer can be ignored, but when the frequency exceeds 50 MHz, the interconnection relationship must be considered, and the electrical parameters of the printed circuit board material must also be considered when evaluating system performance. Therefore, the design of high-speed systems must face timing problems caused by interconnection delays and signal integrity (SI) problems such as crosstalk and transmission line effects.

When the operating frequency of the hardware increases, each transmission line on the wiring network may become a transmitting antenna, generating electromagnetic radiation to other electronic devices or interfering with other devices, thus causing confusion in the hardware timing logic. The Electromagnetic Compatibility (EMC) standard proposes basic requirements for solving the electromagnetic radiation interference that may be generated by the actual wiring network of the hardware and resisting external electromagnetic interference.

1 Several basic concepts of high-speed digital circuit design

In high-speed digital circuits, factors that do not need to be considered in low-speed circuits become particularly important due to signal integrity issues such as crosstalk, reflection, overshoot, oscillation, ground bounce, and offset. In addition, as the coupling structure of existing electrical systems becomes more and more complex, electromagnetic compatibility has also become an issue that cannot be ignored.

To solve the problem of high-speed circuit design, we first need to truly understand the concept of high-speed signals. High speed is not determined by the frequency, but by the edge speed of the signal. It is generally believed that a rise time less than 4 times the signal transmission delay can be considered a high-speed signal. Even in a system with a low operating frequency, signal integrity problems will occur. This is because with the improvement of integrated circuit technology, the signal edges of the I/O ports of the devices used are steeper and faster than before, so even if the operating clock is not high, it is still a high-speed device, which brings various problems of signal integrity.

2 Basic requirements for high-speed digital circuit design

In PCB design, the analysis of electromagnetic compatibility is also inseparable from the signal integrity of the wiring network itself. It mainly analyzes the electromagnetic radiation and electromagnetic interference that may be generated by the actual wiring network, as well as the ability of the circuit board itself to resist external electromagnetic interference, and proposes rules for suppressing electromagnetic radiation and interference during layout and wiring according to the designer's requirements as the guiding principle of the entire PCB design process. Electromagnetic radiation analysis mainly considers the electromagnetic radiation at the interface between the PCB board and the external interface, the electromagnetic radiation of the power layer in the PCB board, and the external radiation problem when the high-power wiring network is working dynamically. For high-speed digital circuit design, especially when the digital signal rate on the bus is higher than 50 MHz, the mathematical model of lumped parameters used to analyze EMC/EMI characteristics seems powerless. Designers tend to use mathematical models of distributed discrete parameters for transmission line analysis (TALC) of wiring networks. For electronic systems composed of multiple PCB boards connected by a bus, the electromagnetic compatibility performance between different PCB boards must also be analyzed.

In view of the electromagnetic compatibility and signal integrity issues in high-speed digital circuit design, the following aspects need to be considered when designing high-speed PCB boards. [page]

2.1 Termination Matching

The impedance discontinuity on the transmission line caused by the impedance mismatch between the source and load ends will cause reflection on the signal line. The load will reflect part of the voltage back to the source end, causing the voltage level to rise, which will have a destructive effect on the device. At the same time, since there are inherent inductance and capacitance on any transmission line, if the signal is reflected back and forth on the transmission line, ringing and surround oscillation will inevitably occur, causing circuit timing to be misaligned. Using termination matching at the source or terminal is a better solution.

The important parameters related to signal reflection are analyzed using the ideal transmission line model shown in Figure 1. In the figure, the ideal transmission line L is driven by a digital signal driving source VS with an internal resistance of R0, the characteristic impedance of the transmission line is Z0, and the load impedance is RL.

The mismatch between the load impedance and the transmission line impedance will reflect part of the signal back to the source end (point A) at the load end (point B). The amplitude of the reflected voltage signal is determined by the load reflection coefficient ρL:

Where ρL is called the load voltage reflection coefficient, which is actually the ratio of the reflected voltage to the incident voltage.

From equation (1), it can be seen that -1≤ρL≤+l, and when RL=Z0, ρ1=0, and no reflection will occur. That is, as long as the terminal matching is performed according to the characteristic impedance of the transmission line, the reflection can be eliminated. In principle, the amplitude of the reflected wave can be as large as the amplitude of the incident voltage, and the polarity can be positive or negative. When RLZ0, ρL>0, it is in an underdamped state, and the polarity of the reflected wave is positive.

When the voltage reflected from the load end reaches the source end, it will be reflected back to the load end again to form a secondary reflection wave. At this time, the amplitude of the reflected voltage is determined by the source reflection coefficient ρS:

There are usually two strategies for terminating transmission lines: parallel termination matching at the load end and serial termination matching at the source end. As long as either the load reflection coefficient or the source reflection coefficient is zero, the reflection will be eliminated. Parallel termination eliminates reflection at the load end before the signal energy is reflected back to the source end, even if ρ1=0, eliminating one reflection, which can reduce noise, electromagnetic interference (EMI) and radio frequency interference (RFI); serial termination eliminates the signal reflected back from the load end at the source end, even if ρS=0 and ρL=1 (no matching is added to the load end), only eliminating the secondary reflection. When the level shift occurs, the source end signal will appear a half-wave waveform with a duration of 2TD (TD is the transmission delay from the signal source end to the terminal end), which means that other signal input ends cannot be added along the transmission line, because incorrect logic states will appear within the above 2TD time. The two termination strategies have their own advantages and disadvantages, but since the matching network of the parallel termination needs to be connected to the power supply, it is more complicated to use; the serial termination only needs to connect a resistor in series at the signal source end, which consumes less power and is easy to implement. It has great practical engineering application value, so it is widely used. [page]

2.2 Preventing ground bounce

When many digital signals on the PCB are switched synchronously (such as the CPU data bus, address bus, etc.), the impedance on the power line and the ground line will generate synchronous switching noise (SSN). At the same time, due to the existence of chip package inductance, the large current surge formed during the synchronous switching of the circuit will cause rebound noise (referred to as ground bounce) on the ground plane, so that voltage fluctuations and changes will occur on the real ground plane (0 V), and this noise will affect the operation of other components.

The strength of SSN and ground bounce also depends on the I/O characteristics of the integrated circuit, the impedance of the power layer and ground plane layer of the PCB board, and the layout and wiring method of high-speed devices on the PCB board. The increase of load capacitance, the decrease of load resistance, the increase of ground inductance, and the increase of the number of switching devices will all lead to the increase of ground bounce. In the design of high-speed PCB circuits, the following basic measures can be taken to reduce the impact of SSN and ground bounce:

① Reduce the output flip speed. Some new bus driver devices use embedded circuit design to reduce the flip speed while minimizing the impact on transmission delay.

② Use a separate dedicated reference ground. Since the current of the separate reference ground is very small, the ground reflection phenomenon will be greatly reduced. For the chip with separate ground, it is necessary to ensure that each ground line has the shortest path directly to the ground plane.

③ Reduce the inductance of the system power supply. High-speed circuit design requires the use of a separate power layer and the power layer and ground plane should be as close as possible.

④ Reduce the inductance of the power and ground pins in the chip package. For example, increase the number of power/ground pins, shorten the lead length, and use a large copper area as much as possible.

⑤ Increase the mutual inductance between power and ground. The power and ground pins should be arranged in pairs and as close as possible.

⑥ Add bypass capacitors to the system power supply. These capacitors can provide low-inductance bypass for high-frequency transient AC signals, while slower-changing signals still follow the system power supply loop.

2.3 Reducing crosstalk

The parameters of the PCB board layers, the spacing between signal lines, the electrical characteristics of the driver and receiver, and the line termination method all have a certain impact on crosstalk.

The magnitude of the crosstalk voltage is inversely proportional to the distance between the two lines and directly proportional to the parallel length of the two lines, but there is no multiple relationship. When wiring in actual high-speed circuits, when the wiring space is small or the wiring density is high, the crosstalk problem between signal lines should be treated with caution. The crosstalk of high-frequency signal lines to adjacent signal lines may cause false triggering at the gate level. Such problems are difficult to be discovered and properly resolved during circuit debugging.

As the frequency of the interference source signal increases, the crosstalk amplitude on the interfered object also increases; the rise/fall time or edge change (rising edge and falling edge) of the signal has a greater impact on the crosstalk. The faster the edge change, the greater the crosstalk.

Since devices with fast rise times are increasingly used in the design of modern high-speed digital circuits, even if the signal frequency of such devices is not high, they should be carefully considered during wiring to prevent excessive crosstalk.

The distance between the transmission line and the ground plane (i.e., the thickness of the dielectric layer between the transmission line and the ground plane) has a great influence on the crosstalk. For the same wiring structure, when the thickness of the dielectric layer doubles, the crosstalk increases significantly. For the same dielectric layer thickness, the crosstalk of the strip transmission line is smaller than that of the microstrip transmission line. It can be seen that the influence of the ground plane on transmission lines of different structures is also different. Therefore, when wiring high-speed circuits, if the impedance control of the strip transmission line can meet the requirements, then using the strip transmission line can achieve better crosstalk suppression effect than using the microstrip transmission line.

Therefore, in the layout and routing of high-speed PCB boards, attention can be paid to the following aspects to achieve the purpose of reducing crosstalk:

① Increase the line spacing and reduce the parallel length of the line. If necessary, the line can be routed in a jog manner, that is, for two signal lines with a long parallel length, the spacing can be discontinuously pulled apart during wiring. This can not only save tight wiring resources, but also effectively suppress crosstalk;

② When the high-speed signal line meets the conditions, adding termination matching can reduce or eliminate reflection, thereby reducing crosstalk;

③ For microstrip transmission lines and strip transmission lines, limiting the trace height to within 10 mil (1 000 mil = 25.4 mm) above the ground plane can significantly reduce crosstalk;

④ If the wiring space allows, inserting a ground wire between two wires with severe crosstalk can serve as an isolation, thereby reducing crosstalk.

⑤ During the wiring process of the same transmission line, try to minimize the use of vias, because the presence of vias will have a greater impact on the characteristic impedance of the transmission line.

⑥ In PCB layout and wiring design, try to place closely connected devices close to each other to reduce the length of the transmission line. At the same time, measures such as clock line isolation, equal length of differential line pairs, and daisy-chain connection of data/address buses should be used to achieve better signal integrity results. [page]

2.4 Reduce electromagnetic interference

Electromagnetic interference is mainly divided into two categories: conducted interference and radiated interference. As long as the source and propagation path of the interference source are cut off, the electronic equipment can meet the requirements of electromagnetic compatibility. In the actual design of PCB boards, the following issues should be paid attention to:

① In actual design, it is recommended to use physical ground and power layers to avoid the power and ground being split, which may lead to complex current loops. The larger the current loop, the greater the radiation, so it is necessary to avoid routing any signal, especially the clock signal, on the split ground.

② Place the clock driver in the center of the circuit board instead of the periphery. Placing the clock driver on the periphery of the circuit board will increase the magnetic dipole moment.

③ In order to further reduce the EMI of the top-layer clock signal line, it is best to lay ground lines in parallel on both sides of the clock line. Of course, it is best to lay the clock signal on the internal signal layer between the ground layer and the power layer.

④ The clock signal uses a wiring width of 4 to 8 mils, because narrow signal lines are more likely to increase high-frequency signal attenuation and reduce capacitive coupling between signal lines.

⑤ Since right-angle wiring will increase wiring capacitance and increase impedance discontinuity, thereby causing signal degradation, right-angle wiring and T-type wiring should be avoided as much as possible.

⑥ Try to meet impedance matching. In most cases, impedance mismatch will cause reflection, and signal integrity also depends mainly on impedance matching.

⑦ The clock signal wiring cannot be too long in parallel with other signal lines, otherwise crosstalk will occur, resulting in increased EMI. A better way is to ensure that the spacing between these lines is not less than the line width.

3 High-speed digital circuit design simulation examples

It is very difficult to analyze and find signal integrity problems on an existing PCB board. Even if the problem is found, it will take a lot of time and money to implement an effective solution on a formed board. Therefore, we hope to find, discover, and eliminate or improve signal integrity problems during the circuit design process before the physical design is completed. This is the task that EDA tools need to accomplish. Advanced EDA signal integrity tools can simulate various parameters in actual physical design and conduct in-depth and detailed analysis of signal integrity problems in the circuit.

The new generation of EDA signal integrity tools mainly include pre-wiring/post-wiring SI analysis tools and system-level SI analysis tools. Using pre-wiring SI analysis tools can help designers select components, adjust component layout, plan system clock networks, and determine termination strategies for key lines before wiring, based on the design's requirements for signal integrity and timing. SI analysis and simulation tools can not only analyze the signal flow of a PCB board, but also analyze other components in the same system (such as backplanes, connectors, cables and their interfaces). This is a system-level SI analysis tool.

SI analysis tools for system-level evaluation can analyze system components such as multiple boards, connectors, cables, etc., and can help designers eliminate potential SI problems through design suggestions. They generally include IBIS model interface, 2D transmission line and crosstalk simulation, circuit simulation, and graphical display of SI analysis results. This type of tool can comprehensively consider the impact of these factors on SI and the mutual influence between these factors in various fields included in the design, such as electrical, EMC, thermal performance, and mechanical performance, so as to conduct true system-level analysis and verification. For example, Mentor Graphics' HyperLynix and ICX design tools can perform board-level simulation and line-level simulation of signal lines driven by timing and electrical rules, and provide multi-board analysis functions. They are typical system-level SI tools.

Figure 2 shows a comparison of the design before and after the modification when using HyperLynix for PCB signal integrity analysis, as well as the corresponding EMC/EMI improvements.

Figure 2(a) shows the case where no matching resistor is added. It can be clearly seen that the waveform at output terminal A has a large undershoot (about 1 V), and the maximum amplitude of the waveform has reached 4 V (I/O signal is 3.3 V), with obvious reflection superposition. The waveform at input terminal B is quite bad. The signal amplitude of the undershoot and overshoot points caused by reflection is close to the threshold level. Such a clock signal can easily cause erroneous operation of the trigger. Figure 2(b) shows the waveform after adding a 47 Ω matching resistor close to the source output. It can be seen that the waveforms of A and B have been significantly improved.

Conclusion

Nowadays, IC manufacturing technology is developing at a rapid speed of Moore's Law, which puts forward higher requirements for high-speed PCB design. The various simulation results provided by advanced EDA simulation tools are very close to the actual situation, which plays a guiding role in high-speed digital circuit design, greatly reducing the design cycle and repetitiveness, and also provides theoretical guidance for the specific debugging of the circuit.