A FIR filter design scheme based on FPGA parallel pipeline

1 FIR filter principle

Finite impulse response (FIR) digital filters and infinite impulse response (IIR) digital filters are widely used in digital signal processing systems. IIR digital filters are convenient and simple, but their phase is nonlinear, requiring the use of an all-pass network for phase correction, and stability is difficult to guarantee. FIR filters have excellent linear phase characteristics, making them increasingly popular. FIR digital filters are linear time-invariant systems (LTI). N-order causal finite impulse response filters can be described by the transfer function H(z).

In the time domain, the input and output relationship of the above finite impulse response filter is as follows:

Where x[n] and y[n] are the input and output sequences respectively.

An N-order finite impulse response filter is described by N+1 coefficients and is usually implemented by N+1 multipliers and N two-input adders. The coefficients of the multipliers are exactly the coefficients of the transfer function, so this structure is called a direct structure and can be implemented by equation (1.2).

When the impulse response meets the following conditions, the FIR filter has a symmetrical structure and is a linear phase filter:

This symmetry can halve the number of multipliers: for an n-valued filter, when n is an even number, the number of multipliers is n/2; when n is an odd number, the number of multipliers is (n+1)/2. In circuit implementation, multipliers occupy a large number of logic units. The increase in multipliers means an increase in circuit cost and also affects the operating speed of the circuit.

The unit impulse response filter of an N-order linear phase causal FIR system can be expressed as a symmetrical impulse response

To describe. [page]

The impulse response of a FIR transfer function with a symmetrical impulse response can be written as follows:

When N is an even number

Then the structure of the FIR linear phase system can be transformed into that shown in FIG. 1(a) and FIG. 1(b).

2 Filter Design Scheme

With the increasing application of digital technology, ASIC devices represented by field programmable gate arrays (FPGAs) have been rapidly popularized and developed, and the device integration and speed are growing at a high speed. FPGAs have both the high logic density and high reliability of gate arrays and the user-programmable characteristics of programmable logic devices, which can reduce the risks of system design and maintenance, reduce product costs, and shorten the design cycle.

Distributed algorithm is a method of operation for the purpose of realizing multiplication and addition. The difference between it and the traditional algorithm in realizing multiplication and addition is that the order of executing partial product operations is different. Simply put, when completing the multiplication and addition function, the distributed algorithm adds the partial products generated by each corresponding bit of each input data in advance to form the corresponding partial products, and then accumulates the partial products to form the final result, while the traditional algorithm waits until all products are generated before adding them to complete the multiplication and addition operation. Compared with the traditional algorithm, the distributed algorithm can greatly reduce the scale of hardware circuits, easily implement pipeline processing, and improve the execution speed of the circuit.

FPGA has a regular internal logic block array and rich connection resources, which is particularly suitable for digital signal processing tasks with fine-grained and highly parallel structure characteristics, such as FIR, FFT, etc. The design process of FIR filter is implemented using FPGA, and the key technology in the design, distributed algorithm, is described in detail.

The structure of FIR filter is mainly non-recursive structure, without feedback from output to input. And FIR filter can easily obtain strict linear phase characteristics, avoiding phase distortion of the processed signal. The linear phase is only the time delay of h(n) in the time domain. This feature is very important in waveform transmission systems such as image signal processing and data transmission. In addition, it will not cause blocking phenomenon, which can avoid strong signal drowning weak signal, so it is particularly suitable for situations where the signal strength is very different. [page]

The method of designing FIR filters using window functions is usually simple, but the design of these filters is not optimal. First, the fluctuations in the passband and stopband are basically equal. In addition, for most window functions, the fluctuations in the passband or stopband are not uniform, and usually decrease when leaving the transition band. If the fluctuations are allowed to be evenly distributed throughout the passband, smaller peak fluctuations will be generated. For linear phase causal FIR filters, its series has a central symmetric characteristic, that is, h(i)=±h(N-1-i). Let s(i)=x(i)±x(N-1-i), for even symmetry, substitute into formula (1) to obtain:

According to the requirements, a 9th-order linear phase FIR filter with 8-bit input and 8-bit output is designed, so the method of Figure 2(a) is adopted, where the input signal range is: [99, 0, 0, 0, 99, 0, 0, 0, 99, 0, 0, 0, 99, ...], the Fs of this filter is 100kHz, and the Fc is 10kHz. The coefficients and amplitude-frequency response of the 9th-order FIR filter designed and calculated using MATLAB are as follows:

After integerization, the parameters of the FIR filter are: [4c, 4f, 50, 52, 52, 52, 50, 4f, 4c:]

According to the above ideas, the schematic diagram of the FIR filter can be designed as follows:

Next, we analyze the output bit number of each adder and multiplier. For the first-stage adder, the input is 8 bits and the output is uniformly 9 bits. The last adder has three inputs, all of which have 8 bits and 10 bits. Analyze each multiplier. The first multiplier is 4c, so the input is 9 bits and the output is 15 bits. The second multiplier is 4f, with a 9-bit input and a 15-bit output. The third multiplier is 50, with a 9-bit input and a 15-bit output. The fourth multiplier is 52, with a 10-bit input and a 16-bit output. Add the output results of the multipliers in pairs. The first adder has a 15-bit input and a 16-bit output. The second adder has 15-bit and 16-bit inputs and outputs. The sum of the last two outputs is 16 bits. Discard the last 8 bits and add them together, and the total output is 8 bits. At this point, the input and output of all devices have been determined. Now we enter the module design stage. [page]

3 Module Design

The designed FIR filter consists of 10 small VHD files and one overall BDF file. The VHD file can be divided into the following three modules: register, adder, and multiplier.

3.1 Register Design

The register is used to store a set of binary codes. The triggers of the register are only required to have the functions of setting 1 and setting 0. Therefore, D flip-flops are used to form registers in this design to realize the storage function.

The input signal is accepted before the positive edge of CP, and the flip is triggered when the positive edge occurs. The input is blocked after the positive edge.

Register waveform simulation

3.2 Adder

When adding two multi-bit binary numbers, each bit except the lowest bit should take into account the carry from the lower bit, that is, add the addends of the two corresponding bits and the carry from the lower bit. This operation is called full addition, and the circuit used is called a full adder.

It realizes the addition operation of two binary numbers. When the rising edge of the clock is reached, the two numbers are input, the operation is performed, and the result is output.

Waveform simulation of adder

3.3 Multiplier

Considering resources and speed, constant coefficient multiplication can be implemented by shift addition. Decompose the constant coefficient into the sum of several powers of 2. The following example is a 4C multiplication circuit design. Implement the multiplication of two binary numbers with signed data and fixed data. When the clock rises, the two numbers are input, the operation is performed, and the result is output.

Waveform simulation of multiplier

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4 FIR filter overall circuit

The overall circuit of the FIR filter is basically similar to its schematic diagram. The overall circuit is shown in the figure below:

5 FIR filter overall circuit simulation results

When the input signal is [99, 0, 0, 0, 99, 0, 0, 0, 99, O, 0, 0, 99. …], the actual simulation waveform of the filter is shown in the figure below:

Because the filter is of ninth order, the total delay of the signal passing through each level of trigger, adder and multiplier is 13 clock cycles, so there is no signal output in the first 13 clock cycles in the simulation. The theoretical output sequence obtained by simulating the filter through matlab is: [33, 28, 34, 50, 33, 28, 34, 50, 33, 28, 34, 50, 33, 28, 34, 50……． ] Compared with the actual simulation waveform, the waveform is basically consistent, but because the filter is only of ninth order, there is a certain error with the theoretical value.