Design and implementation of I2C bus in FPGA-based video acquisition

With the development of science and technology and the changes in modern warfare conditions, the single service provided by traditional image signals can no longer meet the needs of modern warfare. Image signals contain extremely rich information, have the characteristics of high communication efficiency, easy recording, realistic images, and strong sense of presence. The amount of information transmitted far exceeds that of other communication methods, so they are receiving more and more attention. Under the JPEG2000 system, the video acquisition system is the FPGA (field programmable gate array) front-end system of the video acquisition function, and is the front channel for video image processing and application. As an important component of the video acquisition system, the I2C (Inter Integrated Circuit) bus was successfully developed by Philips of the Netherlands in the 1980s. It is a simple, bidirectional, two-wire synchronous serial bus hardware interface.

1I2C bus characteristics and protocols

As a serial bus standard, the I2C bus protocol does not have the data throughput capacity of a parallel bus, but its characteristics and protocols make it widely used. Its characteristics and protocols mainly include:

Only two buses are needed, namely the serial clock line (SCL) and the serial data line (SDA), which reduces the number of IC pins. All devices connected to the bus have unique addresses, and the addresses are set by the slave node software. The master node can send or receive data. It is a true multi-master bus. When two or more master nodes initiate data transmission at the same time, conflict detection and arbitration can be used to prevent data from being destroyed. The serial 8-bit bidirectional data transmission rate can reach 100 Kb/s in standard mode, 400 Kb/s in fast mode, and 3.4 Mb/s in high-speed mode. The number of ICs connected to the same bus is only limited by the maximum capacitance of the bus (400 pF). The on-chip filter can filter out the burr waves on the bus data line to ensure data integrity.

Generally, data transmission can only start when the bus is not busy. During data transmission, whenever the clock line is high, the data line must remain stable, and the data line and clock must remain at a high level. When the clock line is high, the change of the data line will be considered as the start or stop of the transmission. Here, the change of the data line from high to low determines the start condition. And the change of the data line from low to high determines the stop condition. After the start condition is met, the serial data line (SDA) is allowed to change during the period when the serial clock line (SCL) is low, but one clock pulse is required for each bit of data. When the serial clock line (SCL) is high, the serial data line (SDA) must be stable and no changes can occur. The master controller releases the serial data line (SDA) line high during the high level of the response clock pulse, and the control is transferred to the receiver . The controlled device must pull down the serial data line (SDA) line during the high level of the response clock pulse, so that the stable low level is regarded as a valid response.

2 System Structure Design

There are some programmable video input processing chips , such as SAA7111 , which are configured through the I2C bus. This bus interface protocol solves many interface problems encountered when designing digital control circuits , greatly reducing the design difficulty of the video input processing part. Therefore, it is widely used in video desktop systems, image multimedia, digital television, image processing, video phones and audio. As the input processing part of the video, the SAA7111 chip is used to digitize the analog input video signal. When the system is powered on, the FPGA first reads the configuration data from the external configuration chip and enters the working mode. Then the I2C configuration module completes the initialization of SAA7111. After the initialization is completed, the FPGA waits for the command to capture the image. After the FPGA receives the capture command, the video signal will enter the video decoder SAA7111 for A/D conversion to convert the analog information into standard YUV digital image information. The system function block diagram is shown in Figure 1.

3 Implementation of I2C bus

In the design of I2C bus, the working mode register of SAA7111 is set through the I2C interface to realize its function. SAA7111 is a powerful analog front end and digital video decoder, which is often used in highly integrated circuits of embedded video applications. It contains two analog processing channels, which can realize video source selection, anti-aliasing filtering, A/D conversion, automatic embedding, automatic gain control, clock generation, multi-standard decoding, and brightness, contrast and saturation control, so as to decode analog composite video data of different standards such as PAL and NTSC into digital signals of brightness, chrominance and related synchronization. There are 32 registers in SAA7111 (SLLbaddress00~1FH), 22 of which are programmable. Among them, OOH, 1A~lCH, lFH are read-only registers. 00H describes the chip version information; 1A~1CH is the text information detection and decoding register, which is rarely used; lFH is used to describe the status of the chip. 02H~12H are readable/writable registers, among which: 02H~05H are analog input control registers, 02H is used to set the analog video signal input mode (8 types in total); 03H~05H are used to set the gain control mode; 06H~12H are mainly used to set the decoding mode. By configuring these registers, the start and end positions of the line synchronization signal can be set, and the brightness, chroma, saturation and the format of the output image data signal can be determined. 01H, 13H~19H, 1DH~1EH registers are reserved for use.

Since each register of SAA7111 is in an uncertain state after power-on reset, the I2C bus protocol needs to be used by FPGA as the master to set the relevant registers of SAA7111. After analog processing, the video image signal input from one of the four analog input terminals AIll, AI12, AI21, and AI22 of SAA7111 can be output to the AOUT terminal for monitoring through the buffer , and the other path can generate digital chrominance signal and brightness signal after passing through the A/D converter . After the brightness signal processing and the color signal processing are performed respectively, one path of the brightness signal processing result will be sent to the color signal processor for comprehensive processing, and the generated Y and UV signals will be formatted and output from VPO (16 bits); the other path will enter the synchronization separator and generate the corresponding line and field synchronization signals HS and VS through the digital PLL . At the same time, the PLL will drive the clock generator to generate HS-locked clock signals LLC and LLC2. All functions of SAA7111 are completed under the control of the I2C bus. The corresponding register initialization values ​​of SA-A7111 are shown in Table 1.

[page]

The I2C bus control read/write operation process is shown in Table 2 and Table 3 (S: start, Sr: restart, P: stop, -S: slave device, -M: master device, W: write bit, R: read bit):

The following four functions are mainly implemented in the design: start condition function, byte transmission function, response condition function and stop condition function. The timing of the four function signals and the data bus transmission are shown in Figure 2 and Figure 3.

In order to meet the above requirements and functions, this paper uses the VHDL language to write logic to simulate the I2C bus interface timing logic. The configuration data can be sent by the host or stored in advance. At the same time, the VHDL is used to write the timing logic to initialize the SAA7111. According to the design requirements, the serial clock line (SCL) and the serial data line (SDA) are designed under different processes. The clock signal source uses a 10 MHz crystal oscillator , which is used as a process excitation signal after frequency division, which can basically meet the data rate requirements of the SAA7111 chip. However, if in some higher-speed situations, the controlled device needs to be quickly set through the I2C bus. Here, only the frequency of the line clock line (SCL) and the serial data line (SDA) needs to be modified. The interface control is shown in Figure 4.

[page]

4 Design Simulation Results

In the design, QuartusⅡ integrated environment is used to implement the I2C bus and simulate the symbol integrated in SAA7111 using VHDL language. The reset signal is an external reset signal, and the clock signal is connected to the required frequency clock signal (clk) as required, and the signal is divided by 16 as the process excitation signal (clkin) as required. For the above initialization data, the simulation waveform is shown in Figure 5. After the simulation result is output correctly, the input/output pins that are consistent with the circuit design are configured. According to the test results, the design can stably and reliably control the parameters of SAA7111. If modification is required, just change the parameters in the program and compile and download again.

5 Conclusion

This design has been applied in the video acquisition and processing system. The I2C bus interface data acquisition is correct and stable, and in the implementation process, it occupies less resources, only 40% of the total resources. The core device is used in conjunction with the image data acquisition chip to save the general I/O interface of the core processing chip, making the overall system circuit very simple, highly reliable, highly integrated, and convenient to interface.