Research on the Design and Optimization of Intelligent Video Surveillance Terminal Based on DSP

1 Introduction

With the development of electronic and computer technology, video surveillance systems are developing from analog technology to digital technology. From the perspective of hardware, the development of video surveillance technology has gone through three stages: analog video signal monitoring, digital video surveillance with PC plus video card, and digital video surveillance based on embedded technology [1]. The monitoring system based on PC technology adopts an integrated method of plugging a video capture card into an ordinary PC. The video card completes image acquisition, digitization and data compression, and the PC is interconnected through a network card and communication equipment. This type of system has currently occupied the mainstream of the market. With the development and maturity of embedded chip technology and embedded operating systems, video surveillance systems based on embedded architecture have attracted more and more attention due to their superior performance such as small size, stable performance and easy installation [2]. As for the research on embedded video surveillance systems, foreign countries started early and existing products have good performance, but the price is expensive and domestic users generally cannot afford it. my country has started research in this area in recent years. Judging from the existing research results, its monitoring terminals are more about integrating imaging systems, video digitization systems and network interfaces [3], but the degree of intelligent monitoring is far from being developed and applied.

Based on the current application background and technical support, this paper designs a new type of embedded intelligent network video surveillance terminal with intrusion scanning function. This monitoring terminal has video acquisition and video detection functions, with Ethernet interface, TCP/IP protocol stack, WEBServer, and can be directly connected to the Internet. Authorized users on the Internet can use a standard browser to access this terminal according to the IP address and view the detected target image. Compared with the traditional monitoring terminal based on PC + video capture card mode, this terminal is small in size, low in cost, easy to install, and has a small amount of data transmitted by the system. It has the function of intelligent detection of moving targets and can be unattended, which is very suitable for security prevention of homes, residential areas, banks, warehouses and other units.

2 System composition and working principle

In order to realize the real-time video detection and network transmission functions, this monitoring terminal adopts the ARM+DSP system framework. The system composition is shown in Figure 1, which mainly includes the main control and network transmission module with ARMS3C4510B as the core, the video acquisition module with SAA7111 as the core, the video detection module with DSPTMS320C6202 as the core, the control module with CPLDEPM7128 as the core, and the power management module, etc. The system has the functions of video acquisition, video detection, image data packaging, network transmission, and control. The working process is as follows: the main control CPU S3C4510B is powered on and initialized, SAA7111 is initialized, S3C4510B system self-checks, TMS320C6202 program is loaded into RAM, DSP is started, and SAA7111 initial parameters are set. After the analog signal of the camera is collected and cached, DSP and its peripheral circuits detect moving targets, and pass the detection results to S3C4510B through the HPI interface of DSP. S3C4510B packages the data, establishes a socket communication server, and waits for connection to send it over the network.

3 Hardware Design

3.1 S3C4510B and its peripheral circuit design

This terminal uses the S3C4510B chip developed by SAMSUNG as the main controller. S3C4510B is a high-performance ARM architecture 32-bit embedded microprocessor with strong real-time multi-task support and expansion capabilities, as well as a series of characteristics such as small size, low power consumption, and high performance. The Ethernet controller with built-in dual-channel buffered DMA and extremely strong peripheral expansion capabilities are the important reasons for choosing it in this design. S3C4510B and peripheral chips FlASH and SDRAM memory form the core of the entire system, responsible for controlling and coordinating the work of each module. This design expands the SDRAM and ROM inside the S3C4510B, and MX29L3211 is used for FLASH, with a capacity of 4MB. MICRO's MT48LC4M16A2TG is used for external SDRAM, with a capacity of 8MB.

The communication circuit design between S3C4510B and TMS320C6202 is implemented by 16-bit host interface (HPI). HPI uses parallel bus interface technology to enable the main control processor to access the internal memory of DSP without DSP intervention. When using HPI to implement data exchange between the main control processor and C6202, data caching, real-time data logging and information processing are allowed. In this design, the host interface (HPI) mainly implements the following two functions: First, when the system starts, the DSP program is loaded. Second, control information is transmitted between S3C4510B and TMS320C6202. S3C4510B responds to the interrupt signal of DSP, reads the image detection results, transfers them to the uClinux operating system, and packages them and sends them to the network.

3.2 Video Capture

The image acquisition device used in this design is a CCD camera. Since the signal output by the CCD camera is an analog signal, the system uses PHILIP's SAA7111 image decoding chip to complete the image digitization process and separate signals such as horizontal and vertical synchronization.

SAA7111 has many functions for users to choose from, and the selection of functions can be completed by setting registers. The research object of this system is based on 256-level grayscale images. The input signal adopts the PAL system. Combined with the specific requirements of the system processing speed, the chip is configured as follows: the YUV4:2:2 signal format is adopted, only the Y (brightness) signal is taken, and the resolution is 256×256 pixels. The I2C bus signal is used to initialize the SAA7111 working register, and then the SAA7111 begins to implement anti-aliasing filtering, linear phase locking, brightness and color separation, video A/D conversion and other functions. At the same time, it generates line synchronization signal HS, field synchronization signal VS, odd and even field mark signal RTSO, pixel clock signal LLC2, and digital video signal. These signals are directly output from the chip pins to decode the analog video signal into a standard YUV format digital video signal [4]. Under the control of the CPLD, it is stored in the FIFO frame memory and stored in the SDRAM through the DSP's DMA channel so that the DSP can perform image processing.

3.3 Logic Control

In the real-time image acquisition and detection work, this system has a lot of problems with logic conversion and logic timing operations such as reading and writing, such as the HF signal of FIFO as the flag signal to start DMA interrupt, the CREE, HS, and VS decoding of SAA7111 to control the write timing of the input data buffer FIFO device, and the Cex signal decoding of DSP to control the read timing of the input data buffer FIFO device. In order to solve the above problems of logic conversion and timing, the system design uses a programmable logic control device CPLD, and selects EPM7128SQC100. This device not only meets the requirements of the corresponding logic timing design, but also provides control signals, and realizes the switching of the system modules required by the gating, buffering, read/write enable, data bus and address bus through programming.

3.4 DSP peripheral circuit design and video detection

In order to realize video detection, the DSP chip TMS320C6202[5] from TI is used. It has 8 parallel processing units, two 16-bit multipliers and 6 arithmetic logic units, 32-bit external memory interface (EMIF: External Memory Interface), and supports interfaces with asynchronous peripherals, asynchronous/synchronous FIFO, PCI bridge, and external master processor. In addition, there are 16-bit host interface HPI and two multi-channel buffered serial ports McBSP (multi-channel buffered serial ports), which can not only complete full-duplex serial communication of standard serial ports, but also support direct interfaces under multiple communication protocols. DSP not only completes real-time video detection, but also operates the 32 registers inside SAA7111 through the I2C bus to complete the initialization parameter setting.

In order to ensure fast and reliable operation of DSP programs, FLASH and high-speed SDRAM are used. Among them, FLASH uses 8MB AM29LV800B produced by AMD to store programs and initialization data, which are imported into C6202 through DSP's EMIF for image processing operations. SDRAM uses 8MB HY57V651620B to cache real-time image data. The EMIF of the C6000 series digital signal processor provides direct support for SDRAM, and the interface is very convenient. When the system is powered on, the DSP automatically loads the program and initialization data from FLASH to the high-speed SDRAM. After loading, the program runs at full speed in the high-speed SDRAM.

Taking into account the speed matching problem during image data acquisition and DSP processing, the system uses a data buffer FIFO device between the image acquisition module and the DSP module. The digital image data generated by the image acquisition module is first buffered in the FIFO, and then the HF and other signals of the FIFO are used as the flag signal to start the DMA interrupt in the DSP. On this basis, the HF of the FIFO is used to start the DMA channel of the DSP to transfer the image data to the SDRAM extended by the DSP, thereby effectively reducing the number of DSP interrupts caused by image data input and improving the efficiency of DSP interrupts.

Since the data provided by SAA7111 of the image acquisition module to the DSP is TTL level, its logic high level is 5V, and the logic high level of the DSP's I/O is 3.3V, an LVTH162245 level conversion device needs to be added between the image data output by SAA7111 and the DSP's I/O to meet the needs of data level conversion.

In this design, grayscale images are collected. In order to realize the intrusion scanning function, it is required to store two images. Considering the real-time detection requirements, change detection based on inter-frame difference is adopted. When detecting moving targets, considering the selectivity of target size and in order to overcome the false alarm caused by illumination changes, the concept of image block is introduced on the basis of inter-frame difference. The image is divided into M n×n sub-blocks, and it is judged whether each sub-block image has changed. The number of sub-blocks that have changed is counted. The judgment formula [6] is:

Sensitive term, α is the suppression coefficient, and N is the number of pixels in the detection area. With this block comparison method, the threshold value range is greatly reduced, easy to determine, and has a certain selectivity for the size of the moving target. When detecting whether each sub-block image has changed, the illumination sensitivity term is introduced to avoid false alarms caused by illumination changes. This method has a certain degree of adaptability to light changes and expands the dynamic application range of the system.

3.5 Network Interface Circuit Design

S3C4510B integrates Ethernet MAC interface controller, so the external network interface only needs to add physical layer chip and RJ-45 interface. This part of the circuit has a detailed circuit design reference in the S3C4510B application manual. The physical layer chip selected in this system is LXT970A (10/100MB), and this monitoring terminal can be easily connected to Ethernet through the RJ-45 interface.

4 Software Design

This terminal uses the uClinux embedded operating system. uClinux is highly portable, supports multitasking, has a complete TCP/IP protocol stack, and supports many other network protocols, which is convenient for developing network applications. The design of the terminal software mainly includes the platform transplantation of the uClinux operating system and the development of drivers and applications for various hardware devices under uClinux.

This terminal software includes applications such as video acquisition, video detection, master control program and network transmission. In order to ensure the normal operation of the system hardware, it also includes hardware initialization program and low-level drivers written for various devices. The tasks that need to be completed in the driver include: initializing and releasing the device and corresponding resources; reading the data sent by the application to the device file and sending back the data requested by the application, etc. The low-level drivers written include: C6202, S3C4510B internal serial port, network interface chip LXT970A, etc. When the embedded operating system starts, it first loads the device driver to complete the initialization of the device, and then calls the application to complete the corresponding function.

5 Conclusion

The network video surveillance terminal designed in this paper can automatically detect intrusion targets and transmit the detected video data through the Ethernet network. This monitoring terminal is small in size, easy to install, flexible in networking, and truly unmanned. It can be used for security prevention in residential areas, banks, warehouses and other units. With the popularization of home LAN, it is bound to have broad application prospects in home remote video surveillance.

The communication circuit design between S3C4510B and TMS320C6202 is implemented by 16-bit host interface (HPI). HPI uses parallel bus interface technology to enable the main control processor to access the internal memory of DSP without DSP intervention. When using HPI to implement data exchange between the main control processor and C6202, data caching, real-time data logging and information processing are allowed. In this design, the host interface (HPI) mainly implements the following two functions: First, when the system starts, the DSP program is loaded. Second, control information is transmitted between S3C4510B and TMS320C6202. S3C4510B responds to the interrupt signal of DSP, reads the image detection results, transfers them to the uClinux operating system, and packages them and sends them to the network.