Design of Serial Peripheral Interface for High-Speed ​​DSP—TMS320LF2407

1 Introduction

The advantages of DSP (digital signal processing) include processing complex operations, being particularly suitable for digital filtering, voice, video, image processing, communication, and high-speed real-time measurement and control systems. It has become an important device in modern information processing technology, greatly promoting academic research, product development, and application in various fields of signal processing and measurement and control. TI's TMS320LF2407 is a dedicated fixed-point DSP chip. Compared with previous products, the biggest difference is that it has a wealth of peripherals, such as SCI, SPI, EV, etc., and adds transaction management capabilities to the advantages of processing data.

The Serial Peripheral Interface (Serial Peripheral InteRFace) is a synchronous serial peripheral interface protocol proposed by Motorola. It is mainly used in EEPROM, FLASH, real-time clock, AD converter, and between digital processing and digital decoders. It includes master/slave modes, has the advantages of less I/O resource occupation, simple protocol implementation, fast transmission speed, ability to send and receive information at the same time, and support for most processor chips. It is a high-speed full-duplex, synchronous communication bus, and only occupies four wires on the chip pins, saving the chip pins. At the same time, it saves space and provides convenience for PCB layout. It is precisely because of this simple and easy-to-use feature that the TMS320LF2407 chip also integrates this communication protocol.

2 SPI interface structure and design principle

2.1 SPI interface structure

The SPI design mainly consists of two parts: microcontroller interface and SPI control interface. The microcontroller interface and SPI control interface are connected together through the three buses of control line, data line and address line. If there are more SPI interface modules outside, the SPI control interface can be used for software programming and setting to realize the expansion of external devices with SPI interface.

The master-slave controller used in TMS320LF2407 communicates. The master controller starts data transmission by outputting the SPICLK signal. For both the master and slave controllers, data is shifted out of the shift register at one edge of SPICLK and latched into the shift register at the opposite edge. If the CLOCK PHASE bit is 1, data transmission and transfer will occur half a cycle before the SPICLK jump. The master controller can start data transmission at any time because it controls the SPICLK signal. The software determines how the master controller detects when the slave controller is ready to send data to start SPI data transmission.

Figure 1 SPI internal structure

2.2 SPI Design Principles

SPI interface is a kind of synchronous serial bus, which can transmit data at high speed and reliably under the synchronous clock signal SCK. It is divided into two transmission modes: master and slave (MASTER/SLAVER). The sending bus in the master mode is the receiving bus in the slave mode: correspondingly, the sending bus in the slave mode is the receiving bus in the master mode. They can receive and send data at the same time. And the sending and receiving operations can be completed through interrupts or query methods.

2.2.1 Working clock

The clock polarity CPOL and the clock phase CPHA control the 4 different clock modes on the clock signal pin. After the device is enabled and activated, before data transmission or during the interval between two bytes of data, SCK is at an idle level. The clock polarity control bit can be used to select whether the idle level is 0 or 1: The clock phase control bit is used to select the sampling moment of the data receiving device. At this sampling moment, the online data must meet the two parameters of setup time and hold time at the same time, so the data sending device should move the data out to the data line in advance.

The four different clock modes can provide corresponding transmission protocols to complete data transmission according to the needs of peripherals. There is no priority between them. The master and slave devices on the SPI line must set matching transmission timing modes according to the specific situation. Only when the timing matches can data transmission proceed normally. If the settings do not match, the data receiver and sender may act on the same clock edge, resulting in data output failure.

Figure 2 is the data transmission timing when CPHA=0. It includes both CPOL=0 and CPOL=1. When CPOL=0, the data to be transmitted is sent at the rising edge without delay of the clock signal, and the data is received at the falling edge of the clock signal. When CPOL=1, the data is also transmitted without delay, but the difference is that the data is sent at the falling edge and received at the rising edge. Figure 3 is the data transmission timing when CPHA=1. It is similar to Figure 2, but the sampling time is delayed by half a cycle.

Figure 2 CPHA="0 is the SPI bus data transmission timing"

Figure 3 SPI bus data transmission timing when CPHA="1"

3 SPI Hardware Design

Registers play a decisive role in SPI. Whether in microcontroller interface or SPI control interface, registers are the main components in data transmission and control. The most basic and important unit of registers is the trigger. Only by improving the structure of the trigger can the performance of the entire SPI interface be improved.

Some serial interface designs use a B-structure trigger design, in which a simple MOS tube is used as a switch. Although MOS tubes have the advantages of low power consumption and small area, it is becoming increasingly difficult to increase the circuit operating frequency and switching speed. Moreover, if the input signal is not strong, signal backflow is likely to occur, which requires a higher voltage to control the switch. This is also not conducive to data transmission and reducing power consumption.

In order to solve the various problems caused by MOS tubes as switches, and to achieve high-speed information transmission in the TMS320LF2407 serial interface, this design comprehensively considers the influence of factors such as speed, working voltage, and noise tolerance. A novel trigger structure (Figure 4A) is adopted. Most of the interface circuits in this article use the circuit design of this trigger. The working voltage is reduced to 3.3V, which greatly reduces the overall power consumption; a three-state gate is used in the switch to effectively prevent signal backflow and achieve stable signal transmission; a feedback signal is added, and the required feedback signal can be input again when needed; at the same time, the switching rate is accelerated, and the load-carrying capacity is also enhanced.

Figure 4 Comparison of triggers A and B

4 RTL-level design

As the complexity of digital system design continues to increase, specifying effective design strategies in the early stages of design is crucial for the entire design. The behavioral description method is a description of the system mathematical model. It includes RTL, algorithm level, and system level descriptions. RTL refers to describing the digital circuit system by describing the flow of data between registers. It is a concept of data flow. Data processing between registers is completed by combinational logic. The RTL level is a higher level of abstraction in Verilog. At this level of abstraction, modules can be implemented according to the designed algorithm without considering the specific implementation details.

4.1 Register overall circuit design

The following is part of the Verilog HDL source code. It describes the function settings of the relevant registers during data transmission: first, the initial values ​​of each register during reset, then the function design of the registers, and the design of the interrupt enable and flag bits generated during data transmission.

4.2 Overall Timing Simulation

Compile the above Verilog code and write the corresponding test code for verification. Figure 5 is the overall timing simulation waveform of the register write operation. It verifies that the above code is correct and feasible.

Figure 5 Overall timing simulation of write operation

5 Conclusion

The innovation of the author of this article is to improve the structure of the hardware trigger. The single MOS tube structure is replaced by a tri-state gate and a transmission gate. It is first applied to the serial peripheral interface of the TMS320LF2407 chip, reducing the operating voltage to 3.3V, speeding up data transmission, and providing corresponding feedback signals, further improving the trigger structure. At the same time, it has good portability. It is fully customizable, and this design runs reliably and achieves the expected effect.