The Choice of ASIC, FPGA and DSP in Software Radio Design

The application fields of ASIC, FPGA and DSP are overlapping, which requires designers to reconsider the device selection strategy in software radio architecture design. This article discusses the important criteria for selecting ASIC, FPGA and DSP from five aspects: programmability, integration, development cycle, performance and power.

Long considered a panacea for base station development, software-defined radio (SDR) architectures have been viewed by some designers as a key solution to supporting multiple wireless protocols within a single infrastructure design as their ability to adapt to new protocols continues to grow.

Until recently, software-defined radio was only a blueprint for most communication system designers, but that is rapidly changing. With 3G wireless services approaching, designers are becoming more interested in implementing software-defined radio architectures into their infrastructure designs.

Implementing Software Radio

Traditional wireless infrastructure designs can be implemented using a combination of ASIC, DSP, and FPGA devices. In these designs, ASICs and FPGAs are usually responsible for handling advanced coding mechanisms such as Reed Solomon coding, Viterbi coding, and Rake receivers, while DSPs are responsible for speech coding and other speech processing tasks.

In the process of shifting from traditional wireless architecture design to software radio design, the functional division between DSP, FPGA and ASIC is also changing. ASIC gradually provides more programmable functions, while DSP and FPGA begin to have the traditional processing functions of ASIC, and the boundaries between the three are becoming increasingly blurred. Therefore, when designers design software radio, they find it difficult to divide the functional boundaries between ASIC, DSP and FPGA.

Designers must now spend considerable effort weighing the following questions: Can functions traditionally implemented by ASICs be better implemented by FPGAs or DSPs? Or are functions traditionally implemented by DSPs more appropriately implemented by FPGAs or ASICs? The core of the problem is how to develop the right selection criteria and effectively evaluate each processing solution.

Criteria selection

Before any criteria can be chosen, it is necessary to give a precise definition of software radio. There are many different definitions of what constitutes a software radio architecture that developers can come up with across the board, but this article will adopt the approach of the Software Radio Forum ( www.sdRForum.org ), which defines software radio as "a radio that is software controlled over a wide frequency range for a wide range of current and future modulation techniques, wideband and narrowband operation, communications security features (such as frequency hopping), and signal waveforms that meet standard requirements."

Historically, digital wireless systems have been implemented in jet aircraft designed with a single air interface standard, using arbitrary programmable devices to evaluate the system based on cost considerations (see Figure 1). In software radio, each major functional component of the radio (including the RF transceiver) has the ability to be reconfigured on the fly to support multiple air interface standards.

The reconfigurable nature of software radio requires that designers change the criteria they need to consider. As pure processing power dominates the current 2G wireless environment, programmable functions are gradually becoming the focus of software radio design applications.

In summary, when choosing an ASIC, FPGA, or DSP, designers should consider the following five important selection criteria. 1. Programmability: The ability to reconfigure the device to perform the desired functions for all target air interface standards. 2. Integration: The ability to integrate multiple functions on a single device, thereby reducing the size of the digital wireless subsystem and reducing hardware complexity. 3. Development cycle: The time to develop, implement, and test the digital wireless functions of a given device. 4. Performance: The ability of the device to complete the specified functions within the required time. 5. Power: The power utilization of the device to complete the specified functions.

Any of the above criteria will have a direct impact on the designer's choice of DSP, ASIC or FPGA. [page]

Programmability

DSP and FPGA can be easily reconfigured to realize various functions of software radio design. Although existing communication ASIC can provide better performance at a lower cost, the programmability provided is very limited.

The key question is whether there is a digital wireless product suitable for specific requirements among the many wireless ASICs. In a pure software radio structure, obviously no ASIC has such a function, but in fact only a few digital wireless designs require such high flexibility. Therefore, the key step in software radio product development is to determine the programmable features required for each function of the system and determine whether the existing ASIC can provide this function.

The processing capabilities of a certain device can be illustrated by the architecture of a base station transceiver that supports both W-CDMA and GSM. Because W-CDMA uses spread spectrum communication technology, many users can share a single radio frequency (RF) channel. The W-CDMA signal occupies a 5MHz bandwidth in each channel between 1,920 and 1,980MHz for the uplink and 2,110 and 2,170MHz for the downlink.

On the other hand, narrowband TDMA technology generally supports only eight users per radio channel in the GSM system. Each channel of narrowband TDMA occupies a 200kHz bandwidth between 890 and 915MHz for uplink and 935 and 960MHz for downlink.

To effectively accommodate the differences between the above standards in a software radio architecture, both the digital up-converter and down-converter of the intermediate frequency (IF) processor must provide programmable channel selection, filter configuration, and sampling ratio adjustment. New multi-standard digital transceiver ASICs from Intersil, Graychip, and Analog Devices offer many programmable features.

For example, Graychip's GC4016 digital down converter can be reconfigured as a 4-channel narrowband down converter with a maximum available baseband bandwidth of 2.25 MHz per channel, or a single-channel wideband down converter with a maximum available baseband bandwidth of 9 MHz. In addition, the GC4016 will also support user-programmable baseband filters and resamplers in each channel, making the device suitable for intermediate frequency processing of a specified structure.

However, if these devices are required to support future upgrades to the yet-to-be-defined 4G wireless architecture, the applicability of ASICs in digital wireless designs will also change. For example, in the wireless field, there is still much disagreement about whether orthogonal frequency division multiplexing (OFDM) technology should be used in 4G system architectures. Many designers believe that OFDM has strong robustness in multipath environments and is compatible with a variety of broadband standards, such as local multipoint distributed service (LMDS) and multichannel multipoint distributed service (MMDS).

However, since the 4G standard has not yet been defined, and the use of any ASIC signal processing devices in this structure will bring unpredictable risks to future upgrades, IF processing must also use FPGA or DSP devices.

As signal processing increasingly comes from digital IF inputs, the processing algorithms in 4G architectures are becoming increasingly specialized, limiting the ability of a single ASIC device to meet the required programmability requirements.

In 3G/GSM wireless applications, W-CDMA uses an error correction mechanism that combines turbo coding and convolutional coding to meet the required bit error rate (BER) performance requirements. On the other hand, GSM uses a combination of convolutional coding and Fire coding as its error correction mechanism, so commercial ASIC devices targeting specific error correction algorithms will no longer be applicable to the GSM platform, and FPGA or DSP implementation is a better choice.

Integration

Another disadvantage of ASIC devices in software radio architecture design is the integration level. With the continuous advancement of ASIC, DSP and FPGA development technology, the functions integrated into a single device have increased dramatically. However, for ASIC, flexibility will decrease as the integration level increases.

For example, an ASIC chip that acts as a digital transceiver is fully applicable to multiple air interface standards, including GSM, IS-136, CDMA2000, and UMTS W-CDMA. If a CDMA chip rate processor is added to the ASIC, the ASIC is no longer applicable to GSM and IS-136. If a modulator or demodulator that supports QPSK, 8PSK, and 16QAM modulation schemes is added to the ASIC, it becomes a valid solution for implementing the CDMA High Speed ​​Data Rate (HDR) specification, but no longer applicable to any other standard.

At this level of integration, multiple ASIC devices are needed to support multiple space interface standards, but this is often impractical.

Compared with ASIC devices, DSP or FPGA devices can easily integrate multiple digital wireless functions without significantly reducing the flexibility of the device.

In the above example, most of the functions provided by the CDMA2000 HDR ASIC can be implemented on Xilinx's XCV1000E, as shown in Table 1. This level of integration generally results in these products having a smaller overall form factor and greater flexibility than ASIC-based devices.

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Development cycle

The flexibility of ASIC devices also has its advantages in the development of software radio products: the existing ASIC algorithm development is already quite complete, which helps to shorten the time to market. Hardware design is a key development process based on ASIC functions, while software development is subject to the generation of program libraries that access the programmable features of the device.

The design development cycle based on DSP or FPGA is much more complicated because software development usually requires much more resources than the corresponding hardware development. Existing optimized general algorithm libraries are helpful to accelerate DSP and FPGA software development, but these algorithms must be integrated together to realize the desired digital wireless functions, so a complete software development cycle is required.

Designers must also be aware of the major differences between DSP and FPGA software development methods. The time to compile an algorithm on a DSP is typically measured in seconds, while the time to synthesize and route a similar algorithm on an FPGA can take hours. For example, Xilinx's typical FPGA routing rate is 400,000 gates per hour, so compiling an XCV2000E with 2 million gates may take half a day to complete.

This makes FPGA design debugging an expensive process, so the FPGA design cycle usually requires more upfront analysis, including multipath simulation and model testing, before routing the device algorithm.

performance

The qualification of any signal processing device in a software radio architecture must include a measure of whether the device can perform the required functions within a specified time. One of the most basic benchmark measurements in such an evaluation is the measurement of the 1,024-point fast Fourier transform (FFT) processing time, as highlighted in Table 2.

In the examples in Table 2, a programmable ASIC clearly outperforms a DSP or FPGA implementation. In general, an ASIC provides the best performance for any given function, and its execution time can be seen in the data table below.

Comparing the performance of DSP and FPGA function implementations is difficult because the architectures of these devices are designed to handle different types of problems. DSPs operate at very high speeds, but can only complete a limited number of processing tasks at a time. On the other hand, FPGAs usually operate at a lower rate than DSPs, but have almost no limit on the number of processing tasks that can be completed at the same time.

To illustrate these differences, consider a simple FIR filter with 16 taps as shown in Figure 2. This filter requires 16 multiply-and-accumulate (MAC) operations per sample.

The DSP has a clock frequency of 300MHz and can complete about 400 million to 500 million MAC operations per second in a reasonably optimized design. This means that the FIR filter of the C6203 series device has a maximum input rate of 31 million samples per second.

But in FPGA, all 16 MAC operations can be executed in parallel. For Xilinx Virtex devices, 16-bit MAC operations require about 160 reconfigurable logic blocks (CLBs), so the design implementation of 16 concurrent MAC operations will require about 2,560 CLBs. XCV300E can easily implement the above configuration and allow the FIR filter to operate at an input sampling rate of 100 million samples per second.

Additional power

ASIC device designs are often optimized to provide excellent power performance. However, the power of most programmable devices will increase dramatically with device utilization and clock frequency, so this factor must be considered when weighing the power allocation of the overall design.

For example, a 4-channel down converter implemented using Altera's 20K600 programmable logic device (PLD) consumes less than 2W of power to achieve an input data rate of 25 million samples per second. Although this power is relatively high, it is still acceptable for the specified application. If the input data rate is increased to 65 million samples per second, the power consumption will reach 5W, which exceeds the power threshold that many digital wireless products can withstand.

Compared with the Altera 20K600, the Analog Devices AD66244-channel down-converter ASIC consumes 700mW at the same input data rate.

At lower speeds, FPGAs typically outperform high-end DSPs in terms of power efficiency. To illustrate this, consider a Dish

The error correction mechanism used by Network in digital video broadcasting. In this system, the multiplexed data with a rate of up to 27.647Mbps is encoded using the Reed-Solomon error correction mechanism, which directly generates 16 parity bytes for every 188 data bytes and generates a maximum composite data rate of 30Mbps.

In 5,000 clock cycles, the TMS320C6203 can decode a 204-byte Reed-Solomon codeword. To achieve the required data throughput, the CPU must be nearly 50% utilized at 300 MHz, consuming approximately 1.53W of power.

In contrast, the Reed-Solomon decoder design implemented on the Xilinx XCV100E consumes only 200mW of power. This is a huge improvement and is comparable to the performance of commercial Reed-Solomon ASICs such as the AHA4011C from Advanced Hardware Architectures. [page]

Device Selection

The results are summarized in Table 3. The power limits for each device category in the table are subjectively set on a scale of 1 to 5, with 1 being a poor choice for that category and 5 being the best choice.

With the above analysis, it is not difficult to get the distinguishing principles of designing software radio using ASIC, FPGA and DSP devices. These principles are summarized as follows: 1. ASIC only needs to provide acceptable programmability and integration level, and can usually provide the best solution for the specified function. 2.

FPGAs provide the best programmable solution for high-speed signal processing functions that are highly parallel or involve linear processing. 3. DSPs provide the best programmable solution for functions that involve complex analysis or decision analysis.