Research on high performance monitoring and direction finding processing platform based on CPCI system

Abstract: A new high-speed parallel sampling technology architecture and a parallel processing embedded hardware architecture based on programmable chip technology and supporting flexible configuration are proposed. The platform integrates multi-channel high-speed acquisition, large-capacity data storage, high-performance DSP and large-scale FPGA tightly coupled real-time processing, etc. It is innovative in comprehensive integration and application, and can ensure the wide full coverage of the frequency domain and continuity of the time domain for multi-mode, multi-rate, and multi-band signal analysis at the signal layer. At the same time, because its hardware provides abundant resource margin, it can meet the needs of multiple standards and protocol analysis at the information layer and cope with its future evolution.

In order to overcome the shortcomings of poor versatility and scalability of traditional monitoring and direction-finding processing systems[1], this paper, based on software radio technology[2], deeply expounds on the high-speed real-time data acquisition required for integrated design and the terminal processing hardware structure required for high-speed real-time analysis and processing. The system can meet the various index requirements of monitoring and direction-finding equipment under the current new system and complex signal environment, and has a high level of multi-system integration efficiency while effectively saving resources and costs. In the process of research, this paper comprehensively considers the advantages and disadvantages of the interface and structural relationship between the current digital processing terminal and different types of CPU (host), and finally selects the design scheme of high-performance monitoring and direction-finding processing platform based on Compact PCI system.

1 System Structure

The platform structure described in this paper is flexible and open. Its main working principle is as follows: large-scale FPGA is used to receive multi-channel high-speed sampling data streams and complete necessary preprocessing; the main control FPGA arbitrates the chip select signals of each FPGA/DSP according to the processing requirements of each signal, and starts synchronously for real-time processing; multiple real-time processing DSPs and the main control FPGA are tightly coupled to form the core of the parallel processing system; finally, the data is sent to the central processing CPU through the local bus interface for further analysis and processing, completing the comprehensive storage management of information, etc. [3]. The system structure block diagram is shown in Figure 1.

2 Specific plans

2.1 High-speed data acquisition

High-speed data acquisition is the primary issue in the research of high-performance monitoring and direction-finding processing platforms [4]. Its design and implementation are guided by demand on the one hand, and also require an overall grasp of all aspects of the system on the other. Reasonable design of analog signal conditioning circuits, high-stability clock generation circuits, high-speed data stream transmission paths, reasonable timing and control logic, and full consideration of signal integrity and electromagnetic compatibility are the basic guarantees for designing a high-performance data acquisition module.

For the high-speed data acquisition that this article focuses on, if a single ADC chip that meets the sampling rate design requirements is directly used, it will bring about problems such as insufficient dynamic range, lack of flexibility, high cost, and greater risk. If you choose to use multiple chips with lower sampling rates to implement high-speed sampling by alternating sampling, the circuit will be more complicated, and the inconsistency of delay and mismatch of gain between multiple ADCs will make it difficult to compound the sampled signals without distortion. In view of this, the design idea of ​​high-speed data acquisition described in this article is: modular design of A/D boards with appropriate sampling rates, broadband, large dynamic data acquisition solutions based on frequency band division and precise synchronous triggering. This technical architecture has the characteristics of modularity and scalability in hardware design, and has the advantages of high equivalent sampling rate and sampling bandwidth not limited by ADC and conditioning circuits in performance. The working principle of the acquisition module is shown in Figure 2.

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High-speed ADCs are high-power devices, and higher sampling rates usually consume more power. In systems using multiple ADCs and multiple channels, the dissipation problem is even more serious. Linear introduced the low-power 14-bit, 125MS/s ADC LTC2261, which consumes 127 mW and operates on a 1.8 V low-voltage analog power supply, providing a 73.4 dB signal-to-noise ratio and 85 dB parasitic-free dynamic range. The ultra-low aperture jitter of 0.17 ps RMS allows it to undersample the intermediate frequency with excellent noise performance. The innovative digital output can be set to full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS. The double-data-rate digital output allows data to be sent on the rising and falling edges of the clock, thereby reducing the number of required data lines by half. In addition, high-resolution digital processing of high-speed signals requires careful design of the clock circuit. Judging from the performance of the LTC2261 and other high-speed 14-bit series ADCs of LTC, a jitter of 0.5 ps can have a significant impact on the SNR when sampling at high speed. It can be seen from formula (1) that the higher the sampling rate and the more conversion bits, the higher the jitter index requirement for the A/D sampling clock.

For LTC2261, 10 ps of clock jitter will produce 0.8 dB SNR loss at an input frequency of 1 MHz. At an input frequency of 120 MHz, the SNR will be reduced to 41.1 dB. This poses a challenge to the design of high-precision clock circuits. Usually, only expensive high-performance voltage-controlled crystal oscillators can guarantee the required performance. The ultra-low noise clock jitter filter LMK04000 series provided by National Semiconductor provides another low-cost option. The filter uses a simple external crystal and cascaded PLLatinum architecture. The RMS jitter of 12 kHz to 20 MHz is 150 fs, and the jitter of 100 Hz to 20 MHz is 200 fs. The clock output signal is LVPECL/2VPECL, LVDS and LVCMOS, which can effectively improve the performance and accuracy of the system. It features a built-in high-performance cascaded phase-locked loop (2 in total), a low-noise crystal oscillator, a high-performance built-in voltage-controlled oscillator, and a low-noise divider and driver. The first phase-locked loop has two different configurations to choose from, either a simple external crystal oscillator or a voltage-controlled crystal oscillator module to perform the jitter filtering function. The second phase-locked loop can use the internal voltage-controlled oscillator to generate a low-noise clock.

2.2 High-speed and high-volume data storage

The higher the sampling rate and resolution, the larger the transmission bandwidth of the converted data stream, and the higher the requirements for real-time scheduling and continuous storage of subsequent data transmission. The commonly used method now is to reduce the transmission rate by expanding the bit width [4-6]. However, if the real-time massive data storage of high-speed data streams is achieved by expanding the bit width, the equipment scale will inevitably increase, and the restrictions on storage depth or continuous acquisition time are also very prominent. This paper studies the storage capacity, access speed, and flexibility of storage area management. Combined with the FLASH storage array, a high-speed and high-flow data storage card based on FLASH memory is designed and implemented. The memory card complies with the CPCI 6U standard and has the characteristics of modularity, standardization, easy expansion and high stability. It solves the problem of real-time storage of continuous and distortion-free sampling data in the coding analysis and protocol parsing stages of digital post-processing. The main research contents include: using FPGA for high-speed signal scheduling and caching to solve the problem of high-speed digital interface; using ultra-large-scale FPGA to realize online configurable and flexible management of storage areas to achieve the goals of high integration, high reliability, and flexible storage area management (supporting redundant backup) of the entire module. The mass data storage subsystem structure thus realized adopts a standardized and modular design, and has the characteristics of high speed, low power consumption, portability, and easy expansion, which can meet the needs of different tasks.

Figure 3 shows a general data storage board with large storage capacity and high transmission bandwidth based on CPCI standard designed in this paper. The board carries one Stratix III E, two Cyclone III FPGAs and 96 NAND FLASH. Stratix III E is the hub of data reception and distribution of the storage board. This device can handle applications with more memory and provide resources for caching data using ping-pong structure. It mainly completes the following functions: providing a differential transmission rate of up to 1 Gb/s; connecting to the PCI bus through the PCI interface chip PCI9656 to realize a 64-bit local bus; and realizing customized high-speed differential data transmission between boards through J4/J5. Two low-cost Cyclone IIIs are connected to 48 NANDs respectively to realize high-speed data distribution and secondary management of NAND arrays. In the design process of high-speed data storage card, opening up the data transmission channel between the host and the storage module is the focus of debugging, which involves the design of PCI local end matching logic in FPGA. A typical matching logic timing based on state machine design is shown in Figure 4.

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2.3 Tightly coupled and flexible parallel processing modules

The computing power of the main processing platform often constitutes a bottleneck for obtaining complete information in the time and frequency domains of broadband signals. This paper discusses a tightly coupled and flexible parallel processing hardware architecture to solve this problem in response to the specific needs of integrated design [3]. Different signal processing modules have different computing characteristics. During the design process, different modules need to be completed in different devices [7]. FPGA settings are flexible, but it is difficult to increase the main frequency, usually only a few hundred MHz, which is far from the thousands of MHz or even GHz of DSP. Therefore, DSP processing is suitable for complex operations and protocol analysis, while FPGA focuses on parallel processing with large computing volume and simple computing structure. It has better performance in designs such as digital down conversion (DDC), matched filters, and FFT, and is easy to develop. At the same time, in order to fully reflect the idea of ​​software radio and meet the requirements of universality and integration, a breakthrough in reconfigurable technology is a must. The hardware reconfigurability of FPGA is a function that GPP and DSP do not have. Therefore, the main processing platform design based on large-scale FPGA + high-performance DSP adopted in this paper is also a prerequisite for ensuring that the system structure has reconfigurable characteristics. At the same time, in order to ensure good connectivity with the various components of this bus-structured platform, and taking into account the scalability of system performance and processing capabilities, this module uses CPCI as the interconnection control bus, and the design follows the CPCI 6U specification, and reserves SRIO (J3) and high-speed custom IO (J4, J5) as channels for high-speed data flow sharing and collaborative processing between modules or board-level chips. The hardware functions of this parallel processing module are relatively independent, which can be conveniently customized according to functional needs. At the same time, these characteristics also determine that the hardware platform has a long service life and saves research and development funds. The principle block diagram of the parallel processing module is shown in Figure 5.

This parallel processing module uses TI's new high-performance 1.2 GHz single-core DSP TMS320C6455 as the core of parallel processing, providing resources for executing multi-channel processing tasks and coping with high-intensity, high-performance applications that execute multiple software at the same time. C6455 perfectly combines high-bandwidth peripheral integration (Gigabit Ethernet MAC), Serial RapidIO (SRIO), DDR2 memory interface running at 553 MHz, and larger memory (L2 memory up to 2 MB) on a unified device. These provide original support for improving the processing efficiency of common algorithms and improving system expansion capabilities, meeting the requirements of integrated high-performance design.

Based on the latest technology, this paper studies the core technologies such as high-speed data acquisition, data transmission, and real-time processing required for the design of a high-performance monitoring and direction-finding processing platform, realizing the organic combination of the versatility of a general system and the pertinence of a dedicated system, and is innovative in integrated integration and application research. On the basis of fully reflecting the resource margin design, the platform has good real-time processing analysis and information synthesis performance, can meet the needs of a variety of application backgrounds and different technical indicators, and has a high degree of flexibility and adaptability in working methods.

References

[1] Liu Xiaogang, Zhang Yuanyuan, Yang Ruliang. High-speed and large-capacity general signal processor based on CPCI bus [J]. Data Acquisition and Processing, 2008, 23(3): 347-351.

[2] Xiang Xin. Software Radio Principles and Technologies[M]. Shaanxi: Xidian University Press, 2008.

[3] Zhu Rangang, Zhong Zifa, Xu Yangming, et al. Application research of broadband parallel processing technology [J]. Modern Defense Technology, 2009, 37(2): 91-94.

[4] Guo Siwen, Gu Leye. Multi-channel large capacity high speed data acquisition system[J]. Journal of Sichuan University, 2001, 38(1): 29-32.

[5] Jia Jinsuo, Gao Meiguo, Han Yueqiu. Design of large-capacity and high-speed data acquisition system [J]. Telecommunication Technology, 2003(6): 60-63.

[6] Huang Chunxing. Timing design and signal integrity analysis of ultra-high-speed data acquisition system[D]. Master's degree thesis of Nanjing University of Science and Technology, 2004.

[7] Zeng Yifang. DSP Development and Application Technology[M]. Beijing: Beijing University of Aeronautics and Astronautics Press, 2008.