Design of Multi-Physiological Parameter Processing System Based on Nios II

Abstract: The construction of a multi-physiological parameter system data processing platform with NiosⅡ soft-core processor as the core, embedding 32-bit Nios II soft-core system in FPGA to control signal acquisition, processing, storage and display functions. NiosⅡ system design is based on NiosⅡ soft core, integrating all interface circuits on the same FPGA, with simple structure, easy to modify and high cost performance.

As medical instruments and equipment develop towards intelligence, miniaturization, serialization, digitization, and multi-functions, the logic control devices in medical equipment have also evolved from medium- and small-scale integrated chips to field programmable gate arrays (FPGAs). The use of FPGA devices can greatly shorten the development cycle of medical equipment and reduce development costs. At the same time, it is also very convenient to modify the design online. Therefore, FPGA is widely used in medical equipment [1].

This paper mainly builds a data processing platform for a multi-physiological parameter measurement system, embedding a 32-bit Nios II soft-core processor in the FPGA to control the transmission, storage and display of data. The main tasks are to customize the hardware system of this data processing platform and write corresponding programs to control the acquisition, storage and display of data.

Using Nios II processor as the core for design, all interface circuits can be integrated on the same FPGA, which has a simple structure. At the same time, by taking advantage of the online configuration of Nios II soft core, the internal structure of FPGA can be changed through software programming to quickly and conveniently expand and upgrade system performance, greatly shortening the system development cycle and improving cost performance.

Overall Design of Multi-Physiological Parameters Measurement System

A complete physiological parameter detection system structure can be divided into three parts: front-end detection circuit, interface part, and data processing platform, which respectively complete the physiological signal acquisition, transmission and signal processing functions. The system hierarchy is shown in Figure 1.

The front-end detection circuit mainly completes the acquisition and quantification of signals. By connecting different sensors, different physiological signals can be collected, including common physiological signals such as ECG signals, pulse signals, and body temperature. After some amplification, filtering, and analog-to-digital conversion, the collected physiological signals are sent to the data processing module through the serial port for processing to obtain the required physiological parameters, and finally displayed or wirelessly transmitted. This article mainly completes the construction of a data processing platform based on FPGA technology.

Design of Data Processing Platform Based on FPGA Technology

This design builds a data processing platform with Nios II soft-core processor as the core. First, it controls the serial port to receive data and stores it in the corresponding storage space. After relevant data processing, it displays the corresponding waveform and parameters by controlling the display peripherals. NiosⅡ is a RISC general-purpose embedded processor soft core based on Harvard structure. It can be combined with user logic and programmed into Altera's FPGA. The processor has a 32-bit instruction set, a 32-bit data channel and configurable instructions and data buffers [2-3]. [page]

Hardware platform construction

In this design, the Nios II soft-core processor is used as the control core, and the basic data processing platform is formed by connecting serial ports, storage devices, and display peripherals. Therefore, the hardware platform shown in Figure 2 is built.

The hardware platform is mainly implemented on the Altera DE2 development board of Terasic. The main components of the system include the NiosⅡ core, on-chip memory, timer, VGA controller, LCD controller, etc., which are all integrated on an Altera Cyclone II FPGA chip. SoPC Builder is used to configure and generate the system on chip. SoPC Builder automatically generates the HDL file of each module, and also automatically generates some necessary arbitration logic to coordinate the work of various components in the system [4].

Customization of NiosⅡ soft core system

Based on the hardware platform constructed in Figure 2, SoPC Builder is used to customize the 32-bit Nios II CPU and the parameterized Avalon interface bus. Then, the required component cores in the platform are appropriately added to meet the functional requirements of the Nios II system, generating the basic customization shown in Figure 3.

Software Design

The software part mainly controls the reception, storage and display of data. In the custom IP core module, some data processing algorithms can be designed, such as digital filtering algorithms, calculation of certain physiological parameter values, including blood pressure values, heart rate, etc. [page]

Design of data receiving module

This design uses the serial port to receive data. The UART serial port module used in Nios II development is a SoPC Builder component, which is included in the Nios II development kit. The development kit also predefines some UART data structures and commonly used UART functions, which makes it easy to program the UART.

First, the parameters of UART need to be set in SoPC Builder, including baud rate, data frame format for transmission, etc. When the hardware design of the system is completed under SOPC Builder, a hardware abstraction layer (HAL) file will be automatically generated as the interface between software and hardware, and the relevant data structure of the UART module will be declared in the excalibur.h header file. The software accesses the hardware through the abstract address mapping interface of the peripheral. This design uses serial port interrupt to receive data, and its process is shown in Figure 4.

Design of data display module

In the Nios II system, VGA is a peripheral IP core. The most important part of the design is the generation of VGA timing, which is the key to normal output display and is included in the VGA controller. The VGA controller is generated using the interface to user logic in SoPC Builder. First, a timing output and RGB signal output module is defined using the hardware description language. The dot clock 25.175MHz is generated by the clock provided by the development board through the phase-locked loop. The phase-locked loop is added to the system through the MegWizard tool. This module implements the dot clock, composite synchronization control signal, composite blanking control signal, horizontal synchronization and field synchronization signals required for VGA output; it also completes the reading of output display commands and color values ​​from the register. The dot clock, composite synchronization control signal, composite blanking control signal and RGB digital signal are input to ADV7123, and the horizontal synchronization, field synchronization and RGB analog signal converted and output by ADV7123 are input to the VGA display. In addition, the hardware description language is used to implement the reading and writing of the register so that the VGA controller port complies with the Avalon interface specification.

The timing control of the VGA module and the output program of the RGB signal are written in HDL language, and the timing simulation results are shown in Figure 5.

[page]

Design of data storage module

The development board used in this design provides rich storage resources, including 8MB of SDRAM, 512KB of SRAM, 4MB of Flash, and an SD card interface. The general GPIO interface can also easily connect to external expansion storage chips.

This paper mainly designs a data processing platform with Nios II soft-core processor as the core. In future designs, data processing algorithms can be further studied, including digital filtering of signals, numerical calculation of parameters, etc.

The data processing platform based on the extremely flexible Nios II processor can be quickly configured and upgraded according to the needs of different hospitals, communities and families by selecting different front-end data acquisition modules and corresponding data processing algorithms. At the same time, it can be connected to the network to achieve remote medical care and information sharing. The use of field programmable gate arrays in the design of modern medical instruments will significantly shorten the development cycle, reduce design risks, reduce costs, improve product reliability and flexibility, and achieve modularization and miniaturization.

References

[1] Xianglin. Application of field programmable gate array in biomedical engineering. Chinese Journal of Clinical Rehabilitation, 2006; 10(25).

[2] Altera.NiosII processor reference handbook.http://www.altera.com, 2005, 5.

[3] Altera.NiosII software developer's handbook.http://www.altera.com, 2005, 5.

[4] Altera.DE2 development and Education board user manual.http://www.altera.com, 2006, 7.