Research on digital system testing based on boundary scan technology

Abstract: This paper introduces the IC chip structure supporting JTAG standard, the boundary scan test principle and the method of controlling the IC chip in a specific functional mode using boundary scan technology. Design ideas and methods are given for a certain functional mode of IC chip, and the design analysis and experimental implementation are carried out using a PCB board with two xc9572 pc84 chips interconnected as an example. Through the experimental implementation, it is shown that the boundary scan technology is easy to debug the circuit system and convenient for system design, and the designed system control logic is simple and convenient, and easy to implement.

Today, microelectronics technology has entered the era of very large scale integrated circuits (VLSI). With the miniaturization of chip circuits and the development of surface mount technology (SMT) and circuit board assembly technology, traditional testing technology faces huge challenges. In this context, in order to improve the testability of circuits and systems, the Joint Test Action Group (JTAG) proposed a new circuit board testing method in 1987 - boundary scan testing, which was accepted by IEEE in 1990 and formed the IEEE1149.1 standard, also known as the JTAG standard [1]. This technology replaces the traditional "physical probe" with a new "virtual probe" to improve the testability of circuits and systems. Due to the high versatility of the JTAG standard, many IC companies now provide IC chips that support the boundary scan mechanism, and even some FPGA and CPLD chips have adopted this technology.

This paper introduces the IC chip structure that supports the JTAG standard, and takes two xc9572_pc84 chips from Xilinx as examples to explore and use boundary scan technology to control the IC chip in a certain functional mode, and designs the JTAG controller of the chip for a certain functional mode of the IC chip.

1 IC chip structure supporting JTAG standard

The core of boundary scan technology is to set up a boundary scan structure between the input and output pins of the IC chip and the core circuit. The JTAG standard defines a 4-wire serial bus [2]. Through these four test lines, the boundary scan unit can be accessed to achieve the purpose of testing the chip core and peripheral circuits. Figure 1 shows the structure of an IC chip that supports the JTAG standard. In the figure, the scan structure consists of a test access channel (TAP), a boundary scan register (BSR), a TAP controller, an instruction register (IR), and auxiliary registers.

1.1 TAP

TAP is a test access channel composed of 4-wire serial test lines. All operations defined by the JTAG standard are controlled by these four test lines. These four test lines are: test clock input line (TCK), test mode selection input line (TMS), test data input line (TDI), and test data output line (TDO).

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1.2 TAP Controller

The TAP controller is the core controller of the boundary scan test and has a 16-state finite state machine. It works synchronously with the TCK signal and responds to the TMS signal. Under the control of the TCK signal and the TMS signal, the TAP controller can choose to use the instruction register scan or the data register scan, and select the various states used to control the boundary scan test. Figure 2 describes the entire state transition process of the TAP controller [3].

Regardless of the current state, as long as TMS keeps 5 TCK clocks at a high level, the TAP controller will return to the Test_Logic_Reset state, so that the test circuit does not affect the normal logic of the IC chip itself. When testing is required, the TAP controller jumps out of this state, selects data register scan (Select_DR_Scan) or selects instruction register scan (Select_IR_Scan) to enter the various states of Figure 2. A standard test process is as follows: the TAP controller captures instruction information in the Capture_IR state, moves in new instructions through the Shift_IR state, and the new instructions become the current instructions through the Update_IR state; then, the current instruction selects the corresponding test data register in the Select_DR_Scan state, captures the response vector of the previous test vector in the Capture_DR state, moves out the response vector in the Shift_DR state, and moves in the next test vector at the same time, and loads the new test quantity in parallel to the corresponding serial data channel in the Update_DR state until the last test vector is moved in. Among them, the Pause_DR state and the Pause_IR state suspend the data shift state; and the four Exit states are unstable states, which provide flexibility for state transitions.

1.3 BSR

BSR is the core of boundary scan technology. It constitutes a boundary scan chain, in which each boundary scan cell (BSC) is composed of a trigger Q and a multiplexer mux. Figure 3 shows the structure of a BC_1 type BSC in the JTAP standard [3].

In Figure 3, SI is the serial input terminal of BSC, which is connected to the serial output terminal SO of the previous device (BSC), and connected in sequence to form a boundary scan chain. The first end of the scan chain is connected to the TDI pin, and the end is connected to the TDO pin. When MODE is 0, the chip works in normal mode. When the chip works in test mode, the test data enters multiplexer 1 (MUX1) through the SI terminal under the control of the shift signal (SHIFT=1), and enters the SI terminal of the next BSC through the SO terminal; when the chip works in capture mode (SHIFT=0), the trigger Q1 will capture the data of the BSR parallel input terminal (DI), send it to the SO terminal, pass the captured data in the scan chain, and recycle the data at TDO, so as to detect the existence of the fault and locate the location of the fault. When MODE is 1, the chip works in update mode, and the data in Q1 enters multiplexer 2 (MUX2) under the action of the update signal (UPDATE), and enters the core of the chip through the parallel output terminal (DO) of the BSR. [page]

1.4 IR

IR is an instruction register that issues various operation codes to various data registers and determines their working mode. Figure 4 shows the structure of an IR unit [4]. As can be seen from Figure 4, the IR unit is composed of a trigger Q1 and a latch Q2. The CAPTURE DATE signal controls the IR loading instruction, and the SHIRFT IR signal controls the shift of the instruction in the IR; the CLK IR signal is a clock signal obtained from TCK, which is used to provide a clock signal for the capture operation and shift operation of the BSR. The UPDATE IR signal is used to load the current instruction into the latch Q2 to determine the operation mode to be executed and the type of test data register to be used.

1.5 Auxiliary Registers

The auxiliary registers include the device flag register and the bypass register. The device flag register is used to store information such as the device manufacturer, device serial number, and device version number. It can be used to identify the manufacturer of the device on the board and to detect whether the correct device has been installed in the correct position on the circuit board. The bypass register is used to bypass the boundary scan unit directly and pass the scan data directly to the next scan device.

2 Digital System Testing Based on Boundary Scan Technology

Digital system testing based on boundary scan technology includes two aspects: one is the IC chip circuit function test and system interconnection test; the other is to use boundary scan technology to control the IC chip in a certain functional mode to facilitate the design and debugging of the circuit system. This article mainly discusses the latter.

2.1 Test system composition

The test system consists of a host (PC), a tester and a PCB experimental board. The tester is connected to the PC through a standard port (RS232) and connected to the test access channel on the PCB board through a serial standard signal cable, as shown in Figure 5.

The PCB board is composed of two interconnected xc9572 pc84 chips from Xilinx. The chip complies with the JTAG interface standard of IEEE1149.1 and has 84 external pins, 4 JTAG pins, 5 VCC pins, 6 VSS pins, and 69 bidirectional data input/output pins. The xc9572 series chip does not implement the asynchronous reset signal pin TRST, so the cable does not need to provide this signal line. The boundary scan register of the device consists of 216 boundary scan cells, of which 9 cells are internal attribute cells, and the remaining 207 cells form 69 boundary scan cell groups [5].

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2.2 Design Analysis and Implementation

2.2.1 Design content and analysis

In the test system shown in Figure 5, two IC chips are required to implement data processing of different functions. In order to achieve time-sharing access to the memory, one of the xc9572_pc84 chips (IC2) can be set to be controlled by the other xc9572_pc84 chip (IC1), so that IC2 enters high-impedance mode (high-impedance mode is one of the optional modes recommended in the JTAG standard) to shield the access to the memory for a period of time. At this time, all output pins of the controlled chip IC2 will be in a floating state, that is, a high-impedance state.

From the state machine of the TAP controller described in FIG. 2 , it can be seen that by changing the input and output states of the IC chip itself, a boundary scan test can be performed or the JTAG interface can be used to put the IC chip into a specific functional mode.

Chips that support the JTAG standard are accompanied by a specific BSDL (Boundary Scan Description Language) description file [3]. The BSDL language is a subset of the VHDL (Very High Definition Language). It describes the boundary scan characteristics of the chip and is used to communicate between manufacturers, users, and test tools, and to provide relevant information for automatic test pattern generation tools and the detection of specific circuit boards. With the support of the BSDL file, the test logic defined by the JTAG standard can be generated. The BSDL file can be combined with software tools for test generation, result analysis, and fault diagnosis.

By analyzing the BSDL file of the xc9572 pc84 chip [6], we can know that:

…

attribute INSTRUCTION_CAPTURE of xc9572_pc84:

entity is \'000XXX01\'&

attribute INSTRUCTION_DISABLE of xc9572_pc84 : entity is \'HIGHZ\'&

attribute INSTRUCTION_OPCODE of xc9572_pc84:entity is

\'BYPASS (11111111),\' &

\'EXTEST (00000000),\' &

\'IDCODE (11111110),\' &

\'INTEST (00000010),\' &

\'SAMPLE (00000001),\' &

\'USERCODE (11111101)\';

…

From this part of the code, it can be concluded that the control code that needs to be written into the instruction register to control the chip to enter high-impedance mode is 11111100. At this time, the bypass register should be selected to bypass the boundary scan register unit so that the scan data can be directly passed to the next scan device.

2.2.2 Design and Implementation

According to the above analysis, it can be concluded that to control the chip from normal working mode to JTAG high impedance state, the following five steps are required:

① Reset. Since the Xilinx 9572_pc84 chip does not have a TRST pin, and the TMS is continuously high when the chip is working normally, the controller needs to receive a low-level signal at the TMS end to enter the reset state and control the TAP controller to complete the reset operation.

② Enter the Shift_IR state. It can be seen from the TAP controller state machine that when five consecutive TCK rising edges cause the TMS end to receive 01100, it enters the Shift_IR state.

③ Write the instruction code into the instruction register. In the Shift_IR state, write the high-impedance state instruction code 11111100 into the instruction register through TDI, which requires 5 TCK cycles. At this time, TMS needs to maintain a low level for 4 cycles.

④ Enter Exit1_IR state. At the rising edge of the fifth TCK in the Shift_IR state, set TMS=1 and enter the Exit1_IR state.

⑤ Enter Update_IR state. After entering Exit1_IR state, set TMS=1 and enter Update_IR state. At this time, the chip enters high impedance state. [page]

According to the above steps, the design concept of the state machine in the digital system [5] is adopted, and the corresponding function blocks are written in VHDL language to control the xc9572_pc84 chip (IC2) to enter the JTAG high-impedance state (due to space limitations, the VHDL source program is not listed), and then the boundary scan test can be performed. After compiling and simulating the VHDL source program, the JTAG control timing waveform shown in Figure 6 can be obtained.

JTAG test technology is a new test technology, which is based on a chip with a JTAG standard interface. Since this chip has some pre-defined functional modes built in, the chip can be placed in a specific functional mode through the boundary scan channel to improve the flexibility of system control and facilitate system design. This article introduces in detail the ideas and methods of using boundary scan technology to control IC chips in high-impedance mode through design examples, and achieves the expected goals through experimental implementation. The test mechanism based on boundary scan technology can be shared at different stages of the product's life cycle. Therefore, the use of boundary scan technology can easily debug and test the circuit system, significantly reducing the product development cycle and cost.

References

1 IEEE std 1149.1-2001: IEEE Standard Test Access Port and Boundary Scan Architecture[S]. New York, USA, 2001

2 Lee Nayes, Larry Lauenger. Addin Boundary Scan Test Cability to an Existing Multi- strategy Tester[J]. Autotestcon, 1993

3 Chen Guangyu, Pan Zhongliang. Testability Design Technology[M]. Beijing: Electronic Industry Press, 1997

4 Yang Tingshan. Boundary scan technology and its application [M]. Measurement and Control Technology, 2000; (199): 5～8

5 Jiang Lidong. VHDL Language Programming and Application [M]. Beijing: Beijing University of Posts and Telecommunications Press, 2001

6 Automated Design Methods for Application-Specific Integrated Circuits and Integrated Systems[M]. Beijing: National Defense Industry Press, 1997

7 Gao Ping, Cheng Li. Digital VLSI Circuit Testing Technology—BIST Scheme[J]. Semiconductor Technology 2003; 28(9): 29-32